From 2d53e54f0e1d8fc4f5c3f637b449427d9a2bef25 Mon Sep 17 00:00:00 2001 From: Andrea Di Biagio Date: Wed, 18 Aug 2021 19:40:35 +0100 Subject: [PATCH] [X86][NFC] Pre-commit tests for PR51494 --- .../llvm-mca/X86/Haswell/adcx-adox-read-advance.s | 130 ++++++++++++++++++++ .../tools/llvm-mca/X86/Haswell/mulx-read-advance.s | 130 ++++++++++++++++++++ .../llvm-mca/X86/Znver2/adcx-adox-read-advance.s | 136 +++++++++++++++++++++ .../tools/llvm-mca/X86/Znver2/mulx-read-advance.s | 136 +++++++++++++++++++++ 4 files changed, 532 insertions(+) create mode 100644 llvm/test/tools/llvm-mca/X86/Haswell/adcx-adox-read-advance.s create mode 100644 llvm/test/tools/llvm-mca/X86/Haswell/mulx-read-advance.s create mode 100644 llvm/test/tools/llvm-mca/X86/Znver2/adcx-adox-read-advance.s create mode 100644 llvm/test/tools/llvm-mca/X86/Znver2/mulx-read-advance.s diff --git a/llvm/test/tools/llvm-mca/X86/Haswell/adcx-adox-read-advance.s b/llvm/test/tools/llvm-mca/X86/Haswell/adcx-adox-read-advance.s new file mode 100644 index 0000000..c101d82 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/Haswell/adcx-adox-read-advance.s @@ -0,0 +1,130 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -timeline -iterations=2 < %s | FileCheck %s + +# PR51494: Missing read-advance for the implicit read of EFLAGS. + +# LLVM-MCA-BEGIN +adcx (%rdi), %rcx +# LLVM-MCA-END + +# LLVM-MCA-BEGIN +adox (%rdi), %rcx +# LLVM-MCA-END + +# CHECK: [0] Code Region + +# CHECK: Iterations: 2 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 17 +# CHECK-NEXT: Total uOps: 6 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.35 +# CHECK-NEXT: IPC: 0.12 +# CHECK-NEXT: Block RThroughput: 0.8 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 3 7 0.50 * adcxq (%rdi), %rcx + +# CHECK: Resources: +# CHECK-NEXT: [0] - HWDivider +# CHECK-NEXT: [1] - HWFPDivider +# CHECK-NEXT: [2] - HWPort0 +# CHECK-NEXT: [3] - HWPort1 +# CHECK-NEXT: [4] - HWPort2 +# CHECK-NEXT: [5] - HWPort3 +# CHECK-NEXT: [6] - HWPort4 +# CHECK-NEXT: [7] - HWPort5 +# CHECK-NEXT: [8] - HWPort6 +# CHECK-NEXT: [9] - HWPort7 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] +# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - 0.50 0.50 - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - 0.50 0.50 - adcxq (%rdi), %rcx + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeeeeeER. .. adcxq (%rdi), %rcx +# CHECK-NEXT: [1,0] .D======eeeeeeeER adcxq (%rdi), %rcx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 4.0 0.5 0.0 adcxq (%rdi), %rcx + +# CHECK: [1] Code Region + +# CHECK: Iterations: 2 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 17 +# CHECK-NEXT: Total uOps: 6 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.35 +# CHECK-NEXT: IPC: 0.12 +# CHECK-NEXT: Block RThroughput: 0.8 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 3 7 0.50 * adoxq (%rdi), %rcx + +# CHECK: Resources: +# CHECK-NEXT: [0] - HWDivider +# CHECK-NEXT: [1] - HWFPDivider +# CHECK-NEXT: [2] - HWPort0 +# CHECK-NEXT: [3] - HWPort1 +# CHECK-NEXT: [4] - HWPort2 +# CHECK-NEXT: [5] - HWPort3 +# CHECK-NEXT: [6] - HWPort4 +# CHECK-NEXT: [7] - HWPort5 +# CHECK-NEXT: [8] - HWPort6 +# CHECK-NEXT: [9] - HWPort7 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] +# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - 0.50 0.50 - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - 0.50 0.50 - adoxq (%rdi), %rcx + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeeeeeER. .. adoxq (%rdi), %rcx +# CHECK-NEXT: [1,0] .D======eeeeeeeER adoxq (%rdi), %rcx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 4.0 0.5 0.0 adoxq (%rdi), %rcx diff --git a/llvm/test/tools/llvm-mca/X86/Haswell/mulx-read-advance.s b/llvm/test/tools/llvm-mca/X86/Haswell/mulx-read-advance.s new file mode 100644 index 0000000..b781ebd --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/Haswell/mulx-read-advance.s @@ -0,0 +1,130 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -timeline -iterations=2 < %s | FileCheck %s + +# PR51494: A read-advance on the implicit read of EDX/RDX was missing. + +# LLVM-MCA-BEGIN +mulxl (%rdi), %eax, %edx +# LLVM-MCA-END + +# LLVM-MCA-BEGIN +mulxq (%rdi), %rax, %rdx +# LLVM-MCA-END + +# CHECK: [0] Code Region + +# CHECK: Iterations: 2 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 21 +# CHECK-NEXT: Total uOps: 10 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.48 +# CHECK-NEXT: IPC: 0.10 +# CHECK-NEXT: Block RThroughput: 1.3 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 5 9 1.00 * mulxl (%rdi), %eax, %edx + +# CHECK: Resources: +# CHECK-NEXT: [0] - HWDivider +# CHECK-NEXT: [1] - HWFPDivider +# CHECK-NEXT: [2] - HWPort0 +# CHECK-NEXT: [3] - HWPort1 +# CHECK-NEXT: [4] - HWPort2 +# CHECK-NEXT: [5] - HWPort3 +# CHECK-NEXT: [6] - HWPort4 +# CHECK-NEXT: [7] - HWPort5 +# CHECK-NEXT: [8] - HWPort6 +# CHECK-NEXT: [9] - HWPort7 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] +# CHECK-NEXT: - - 0.50 1.00 0.50 0.50 - 0.50 1.00 - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: - - 0.50 1.00 0.50 0.50 - 0.50 1.00 - mulxl (%rdi), %eax, %edx + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 0 + +# CHECK: [0,0] DeeeeeeeeeER . . mulxl (%rdi), %eax, %edx +# CHECK-NEXT: [1,0] . D=======eeeeeeeeeER mulxl (%rdi), %eax, %edx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 4.5 0.5 0.0 mulxl (%rdi), %eax, %edx + +# CHECK: [1] Code Region + +# CHECK: Iterations: 2 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 21 +# CHECK-NEXT: Total uOps: 8 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.38 +# CHECK-NEXT: IPC: 0.10 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 4 9 1.00 * mulxq (%rdi), %rax, %rdx + +# CHECK: Resources: +# CHECK-NEXT: [0] - HWDivider +# CHECK-NEXT: [1] - HWFPDivider +# CHECK-NEXT: [2] - HWPort0 +# CHECK-NEXT: [3] - HWPort1 +# CHECK-NEXT: [4] - HWPort2 +# CHECK-NEXT: [5] - HWPort3 +# CHECK-NEXT: [6] - HWPort4 +# CHECK-NEXT: [7] - HWPort5 +# CHECK-NEXT: [8] - HWPort6 +# CHECK-NEXT: [9] - HWPort7 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] +# CHECK-NEXT: - - - 1.00 0.50 0.50 - - 1.00 - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: - - - 1.00 0.50 0.50 - - 1.00 - mulxq (%rdi), %rax, %rdx + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 0 + +# CHECK: [0,0] DeeeeeeeeeER . . mulxq (%rdi), %rax, %rdx +# CHECK-NEXT: [1,0] .D========eeeeeeeeeER mulxq (%rdi), %rax, %rdx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 5.0 0.5 0.0 mulxq (%rdi), %rax, %rdx diff --git a/llvm/test/tools/llvm-mca/X86/Znver2/adcx-adox-read-advance.s b/llvm/test/tools/llvm-mca/X86/Znver2/adcx-adox-read-advance.s new file mode 100644 index 0000000..9f1b4c6 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/Znver2/adcx-adox-read-advance.s @@ -0,0 +1,136 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver2 -timeline -iterations=2 < %s | FileCheck %s + +# PR51494: Missing read-advance for the implicit read of EFLAGS. + +# LLVM-MCA-BEGIN +adcx (%rdi), %rcx +# LLVM-MCA-END + +# LLVM-MCA-BEGIN +adox (%rdi), %rcx +# LLVM-MCA-END + +# CHECK: [0] Code Region + +# CHECK: Iterations: 2 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 13 +# CHECK-NEXT: Total uOps: 4 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.31 +# CHECK-NEXT: IPC: 0.15 +# CHECK-NEXT: Block RThroughput: 0.5 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 2 5 0.33 * adcxq (%rdi), %rcx + +# CHECK: Resources: +# CHECK-NEXT: [0] - Zn2AGU0 +# CHECK-NEXT: [1] - Zn2AGU1 +# CHECK-NEXT: [2] - Zn2AGU2 +# CHECK-NEXT: [3] - Zn2ALU0 +# CHECK-NEXT: [4] - Zn2ALU1 +# CHECK-NEXT: [5] - Zn2ALU2 +# CHECK-NEXT: [6] - Zn2ALU3 +# CHECK-NEXT: [7] - Zn2Divider +# CHECK-NEXT: [8] - Zn2FPU0 +# CHECK-NEXT: [9] - Zn2FPU1 +# CHECK-NEXT: [10] - Zn2FPU2 +# CHECK-NEXT: [11] - Zn2FPU3 +# CHECK-NEXT: [12] - Zn2Multiplier + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] +# CHECK-NEXT: - 0.50 0.50 - - 0.50 0.50 - - - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions: +# CHECK-NEXT: - 0.50 0.50 - - 0.50 0.50 - - - - - - adcxq (%rdi), %rcx + +# CHECK: Timeline view: +# CHECK-NEXT: 012 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeeeER . . adcxq (%rdi), %rcx +# CHECK-NEXT: [1,0] D=====eeeeeER adcxq (%rdi), %rcx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 3.5 0.5 0.0 adcxq (%rdi), %rcx + +# CHECK: [1] Code Region + +# CHECK: Iterations: 2 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 13 +# CHECK-NEXT: Total uOps: 4 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.31 +# CHECK-NEXT: IPC: 0.15 +# CHECK-NEXT: Block RThroughput: 0.5 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 2 5 0.33 * adoxq (%rdi), %rcx + +# CHECK: Resources: +# CHECK-NEXT: [0] - Zn2AGU0 +# CHECK-NEXT: [1] - Zn2AGU1 +# CHECK-NEXT: [2] - Zn2AGU2 +# CHECK-NEXT: [3] - Zn2ALU0 +# CHECK-NEXT: [4] - Zn2ALU1 +# CHECK-NEXT: [5] - Zn2ALU2 +# CHECK-NEXT: [6] - Zn2ALU3 +# CHECK-NEXT: [7] - Zn2Divider +# CHECK-NEXT: [8] - Zn2FPU0 +# CHECK-NEXT: [9] - Zn2FPU1 +# CHECK-NEXT: [10] - Zn2FPU2 +# CHECK-NEXT: [11] - Zn2FPU3 +# CHECK-NEXT: [12] - Zn2Multiplier + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] +# CHECK-NEXT: - 0.50 0.50 - - 0.50 0.50 - - - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions: +# CHECK-NEXT: - 0.50 0.50 - - 0.50 0.50 - - - - - - adoxq (%rdi), %rcx + +# CHECK: Timeline view: +# CHECK-NEXT: 012 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeeeER . . adoxq (%rdi), %rcx +# CHECK-NEXT: [1,0] D=====eeeeeER adoxq (%rdi), %rcx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 3.5 0.5 0.0 adoxq (%rdi), %rcx diff --git a/llvm/test/tools/llvm-mca/X86/Znver2/mulx-read-advance.s b/llvm/test/tools/llvm-mca/X86/Znver2/mulx-read-advance.s new file mode 100644 index 0000000..afa7044 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/Znver2/mulx-read-advance.s @@ -0,0 +1,136 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver2 -timeline -iterations=2 < %s | FileCheck %s + +# PR51494: A read-advance on the implicit read of EDX/RDX was missing. + +# LLVM-MCA-BEGIN +mulxl (%rdi), %eax, %edx +# LLVM-MCA-END + +# LLVM-MCA-BEGIN +mulxq (%rdi), %rax, %rdx +# LLVM-MCA-END + +# CHECK: [0] Code Region + +# CHECK: Iterations: 2 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 17 +# CHECK-NEXT: Total uOps: 2 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.12 +# CHECK-NEXT: IPC: 0.12 +# CHECK-NEXT: Block RThroughput: 2.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 7 2.00 * mulxl (%rdi), %eax, %edx + +# CHECK: Resources: +# CHECK-NEXT: [0] - Zn2AGU0 +# CHECK-NEXT: [1] - Zn2AGU1 +# CHECK-NEXT: [2] - Zn2AGU2 +# CHECK-NEXT: [3] - Zn2ALU0 +# CHECK-NEXT: [4] - Zn2ALU1 +# CHECK-NEXT: [5] - Zn2ALU2 +# CHECK-NEXT: [6] - Zn2ALU3 +# CHECK-NEXT: [7] - Zn2Divider +# CHECK-NEXT: [8] - Zn2FPU0 +# CHECK-NEXT: [9] - Zn2FPU1 +# CHECK-NEXT: [10] - Zn2FPU2 +# CHECK-NEXT: [11] - Zn2FPU3 +# CHECK-NEXT: [12] - Zn2Multiplier + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] +# CHECK-NEXT: - 0.50 0.50 - 2.00 - - - - - - - 2.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions: +# CHECK-NEXT: - 0.50 0.50 - 2.00 - - - - - - - 2.00 mulxl (%rdi), %eax, %edx + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeeeeeER. .. mulxl (%rdi), %eax, %edx +# CHECK-NEXT: [1,0] D=======eeeeeeeER mulxl (%rdi), %eax, %edx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 4.5 0.5 0.0 mulxl (%rdi), %eax, %edx + +# CHECK: [1] Code Region + +# CHECK: Iterations: 2 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 17 +# CHECK-NEXT: Total uOps: 2 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.12 +# CHECK-NEXT: IPC: 0.12 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 7 1.00 * mulxq (%rdi), %rax, %rdx + +# CHECK: Resources: +# CHECK-NEXT: [0] - Zn2AGU0 +# CHECK-NEXT: [1] - Zn2AGU1 +# CHECK-NEXT: [2] - Zn2AGU2 +# CHECK-NEXT: [3] - Zn2ALU0 +# CHECK-NEXT: [4] - Zn2ALU1 +# CHECK-NEXT: [5] - Zn2ALU2 +# CHECK-NEXT: [6] - Zn2ALU3 +# CHECK-NEXT: [7] - Zn2Divider +# CHECK-NEXT: [8] - Zn2FPU0 +# CHECK-NEXT: [9] - Zn2FPU1 +# CHECK-NEXT: [10] - Zn2FPU2 +# CHECK-NEXT: [11] - Zn2FPU3 +# CHECK-NEXT: [12] - Zn2Multiplier + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - - - - - 1.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions: +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - - - - - 1.00 mulxq (%rdi), %rax, %rdx + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeeeeeER. .. mulxq (%rdi), %rax, %rdx +# CHECK-NEXT: [1,0] D=======eeeeeeeER mulxq (%rdi), %rax, %rdx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 4.5 0.5 0.0 mulxq (%rdi), %rax, %rdx -- 2.7.4