From 2d42a192e02af9d89dde356a48270fc7d1ef5b16 Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Wed, 29 Sep 2021 21:42:01 +0300 Subject: [PATCH] [X86][Costmodel] Load/store i8 Stride=2 VF=32 interleaving costs The only sched models that for cpu's that support avx2 but not avx512 are: haswell, broadwell, skylake, zen1-3 For load we have: https://godbolt.org/z/xz6x7c35P - for intels `Block RThroughput: =6.0`; for ryzens, `Block RThroughput: <=2.5` So pick cost of `6`. For store we have: https://godbolt.org/z/xz6x7c35P - for intels `Block RThroughput: =4.0`; for ryzens, `Block RThroughput: <=2.0` So pick cost of `4`. I'm directly using the shuffling asm the llc produced, without any manual fixups that may be needed to ensure sequential execution. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D110709 --- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 2 ++ llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll | 2 +- llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-2.ll | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index cceb0aa..653ae9e 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -5067,6 +5067,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( {2, MVT::v4i8, 2}, // (load 8i8 and) deinterleave into 2 x 4i8 {2, MVT::v8i8, 2}, // (load 16i8 and) deinterleave into 2 x 8i8 {2, MVT::v16i8, 4}, // (load 32i8 and) deinterleave into 2 x 16i8 + {2, MVT::v32i8, 6}, // (load 64i8 and) deinterleave into 2 x 32i8 {2, MVT::v2i16, 2}, // (load 4i16 and) deinterleave into 2 x 2i16 {2, MVT::v4i16, 2}, // (load 8i16 and) deinterleave into 2 x 4i16 @@ -5109,6 +5110,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( {2, MVT::v4i8, 1}, // interleave 2 x 4i8 into 8i8 (and store) {2, MVT::v8i8, 1}, // interleave 2 x 8i8 into 16i8 (and store) {2, MVT::v16i8, 3}, // interleave 2 x 16i8 into 32i8 (and store) + {2, MVT::v32i8, 4}, // interleave 2 x 32i8 into 64i8 (and store) {2, MVT::v2i16, 1}, // interleave 2 x 2i16 into 4i16 (and store) {2, MVT::v4i16, 1}, // interleave 2 x 4i16 into 8i16 (and store) diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll index 1c61ecd..ff84b06 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll @@ -30,7 +30,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 3 for VF 4 For instruction: %v0 = load i8, i8* %in0, align 1 ; AVX2: LV: Found an estimated cost of 3 for VF 8 For instruction: %v0 = load i8, i8* %in0, align 1 ; AVX2: LV: Found an estimated cost of 5 for VF 16 For instruction: %v0 = load i8, i8* %in0, align 1 -; AVX2: LV: Found an estimated cost of 166 for VF 32 For instruction: %v0 = load i8, i8* %in0, align 1 +; AVX2: LV: Found an estimated cost of 8 for VF 32 For instruction: %v0 = load i8, i8* %in0, align 1 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load i8, i8* %in0, align 1 ; AVX512: LV: Found an estimated cost of 3 for VF 2 For instruction: %v0 = load i8, i8* %in0, align 1 diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-2.ll b/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-2.ll index d713d30..8bdb8bf 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-2.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-2.ll @@ -30,7 +30,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 2 for VF 4 For instruction: store i8 %v1, i8* %out1, align 1 ; AVX2: LV: Found an estimated cost of 2 for VF 8 For instruction: store i8 %v1, i8* %out1, align 1 ; AVX2: LV: Found an estimated cost of 4 for VF 16 For instruction: store i8 %v1, i8* %out1, align 1 -; AVX2: LV: Found an estimated cost of 166 for VF 32 For instruction: store i8 %v1, i8* %out1, align 1 +; AVX2: LV: Found an estimated cost of 6 for VF 32 For instruction: store i8 %v1, i8* %out1, align 1 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: store i8 %v1, i8* %out1, align 1 ; AVX512: LV: Found an estimated cost of 4 for VF 2 For instruction: store i8 %v1, i8* %out1, align 1 -- 2.7.4