From 2d33327f9d4c154e7454c2d830c1caa8e6850f4f Mon Sep 17 00:00:00 2001 From: Rosie Sumpter Date: Tue, 16 Nov 2021 11:52:19 +0000 Subject: [PATCH] [LoopVectorize] Print fast-math flags for VPReductionRecipe --- llvm/lib/Transforms/Vectorize/VPlan.cpp | 6 ++++-- llvm/test/Transforms/LoopVectorize/vplan-printing.ll | 4 ++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp index 99e8673..44b5e1d 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp @@ -1210,8 +1210,10 @@ void VPReductionRecipe::print(raw_ostream &O, const Twine &Indent, printAsOperand(O, SlotTracker); O << " = "; getChainOp()->printAsOperand(O, SlotTracker); - O << " + reduce." << Instruction::getOpcodeName(RdxDesc->getOpcode()) - << " ("; + O << " +"; + if (isa(getUnderlyingInstr())) + O << getUnderlyingInstr()->getFastMathFlags(); + O << " reduce." << Instruction::getOpcodeName(RdxDesc->getOpcode()) << " ("; getVecOp()->printAsOperand(O, SlotTracker); if (getCondOp()) { O << ", "; diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll index 9efaae3..fbadb8c 100644 --- a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll +++ b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll @@ -89,7 +89,7 @@ define float @print_reduction(i64 %n, float* noalias %y) { ; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi ir<0.000000e+00>, ir<%red.next> ; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr ir<%y>, ir<%iv> ; CHECK-NEXT: WIDEN ir<%lv> = load ir<%arrayidx> -; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + reduce.fadd (ir<%lv>) +; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + fast reduce.fadd (ir<%lv>) ; CHECK-NEXT: No successors ; CHECK-NEXT: } ; CHECK-NEXT: No successors @@ -254,7 +254,7 @@ define float @print_fmuladd_strict(float* %a, float* %b, i64 %n) { ; CHECK-NEXT: CLONE ir<%arrayidx2> = getelementptr ir<%b>, ir<%iv> ; CHECK-NEXT: WIDEN ir<%1> = load ir<%arrayidx2> ; CHECK-NEXT: EMIT vp<%6> = fmul nnan ninf nsz ir<%0> ir<%1> -; CHECK-NEXT: REDUCE ir<%muladd> = ir<%sum.07> + reduce.fadd (vp<%6>) +; CHECK-NEXT: REDUCE ir<%muladd> = ir<%sum.07> + nnan ninf nsz reduce.fadd (vp<%6>) ; CHECK-NEXT: No successors ; CHECK-NEXT: } -- 2.7.4