From 2cae15162ac31b843fd5d111eb08d7a69aee4d0d Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 6 Mar 2012 21:17:23 +0200 Subject: [PATCH] gfx: drv: save pipe specific panel timing regs to an array We have the same set of panel timing regs for each pipe, so store them to an appropriate array instead of separate variables named after the pipe. The CNTR, CONF, DPLL, PALETTE, MIPI registers are handled specially during restore, so the parts related to those are cleaned up separately in the upcoming patches. The only functional change of this patch is that the CNTR register is saved now before all the above generic registers, but as reading these registers don't have a side-effect this shouldn't be a problem. Signed-off-by: Imre Deak Reviewed-by: Jani Nikula Signed-off-by: Kirill A. Shutemov --- drivers/staging/mrst/drv/psb_drv.c | 19 +-- drivers/staging/mrst/drv/psb_drv.h | 60 +++----- drivers/staging/mrst/drv/psb_powermgmt.c | 231 +++++-------------------------- 3 files changed, 60 insertions(+), 250 deletions(-) diff --git a/drivers/staging/mrst/drv/psb_drv.c b/drivers/staging/mrst/drv/psb_drv.c index 6b60821..e349b11 100644 --- a/drivers/staging/mrst/drv/psb_drv.c +++ b/drivers/staging/mrst/drv/psb_drv.c @@ -1752,7 +1752,7 @@ static int psb_mode_operation_ioctl(struct drm_device *dev, void *data, REG_READ(PSB_DSPSURF(PSB_PIPE_A)); ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND); } else { - dev_priv->saveDSPASURF = psb_fb->offset; + dev_priv->pipe_regs[0].dsp_surf = psb_fb->offset; } return 0; @@ -1949,6 +1949,7 @@ static int psb_register_rw_ioctl(struct drm_device *dev, void *data, unsigned int iep_ble_status; unsigned long iep_timeout; bool force_on = arg->b_force_hw_on; + struct psb_pipe_regs *pipe_regs = dev_priv->pipe_regs; if (arg->display_write_mask != 0) { if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, force_on)) { @@ -1990,13 +1991,13 @@ static int psb_register_rw_ioctl(struct drm_device *dev, void *data, dev_priv->savePFIT_PGM_RATIOS = arg->display.pfit_programmed_scale_ratios; if (arg->display_write_mask & REGRWBITS_PIPEASRC) - dev_priv->savePIPEASRC = arg->display.pipeasrc; + pipe_regs[0].src = arg->display.pipeasrc; if (arg->display_write_mask & REGRWBITS_PIPEBSRC) - dev_priv->savePIPEBSRC = arg->display.pipebsrc; + pipe_regs[1].src = arg->display.pipebsrc; if (arg->display_write_mask & REGRWBITS_VTOTAL_A) - dev_priv->saveVTOTAL_A = arg->display.vtotal_a; + pipe_regs[0].vtotal = arg->display.vtotal_a; if (arg->display_write_mask & REGRWBITS_VTOTAL_B) - dev_priv->saveVTOTAL_B = arg->display.vtotal_b; + pipe_regs[1].vtotal = arg->display.vtotal_b; } } @@ -2041,13 +2042,13 @@ static int psb_register_rw_ioctl(struct drm_device *dev, void *data, arg->display.pfit_programmed_scale_ratios = dev_priv->savePFIT_PGM_RATIOS; if (arg->display_read_mask & REGRWBITS_PIPEASRC) - arg->display.pipeasrc = dev_priv->savePIPEASRC; + arg->display.pipeasrc = pipe_regs[0].src; if (arg->display_read_mask & REGRWBITS_PIPEBSRC) - arg->display.pipebsrc = dev_priv->savePIPEBSRC; + arg->display.pipebsrc = pipe_regs[1].src; if (arg->display_read_mask & REGRWBITS_VTOTAL_A) - arg->display.vtotal_a = dev_priv->saveVTOTAL_A; + arg->display.vtotal_a = pipe_regs[0].vtotal; if (arg->display_read_mask & REGRWBITS_VTOTAL_B) - arg->display.vtotal_b = dev_priv->saveVTOTAL_B; + arg->display.vtotal_b = pipe_regs[1].vtotal; } } diff --git a/drivers/staging/mrst/drv/psb_drv.h b/drivers/staging/mrst/drv/psb_drv.h index 652ba41..ba01c64 100644 --- a/drivers/staging/mrst/drv/psb_drv.h +++ b/drivers/staging/mrst/drv/psb_drv.h @@ -39,6 +39,7 @@ #include "ttm/ttm_bo_driver.h" #include "ttm/ttm_lock.h" #include "psb_irq.h" +#include "psb_intel_reg.h" #ifdef CONFIG_EARLYSUSPEND #include @@ -693,44 +694,37 @@ struct drm_psb_private { /* *Register state */ + struct psb_pipe_regs { + uint32_t htotal; + uint32_t hblank; + uint32_t hsync; + uint32_t vtotal; + uint32_t vblank; + uint32_t vsync; + uint32_t src; + uint32_t dsp_stride; + uint32_t dsp_line_offs; + uint32_t dsp_tile_offs; + uint32_t dsp_size; + uint32_t dsp_pos; + uint32_t dsp_surf; + uint32_t dsp_status; + } pipe_regs[PSB_PIPE_NUM]; + uint32_t saveDSPACNTR; uint32_t saveDSPBCNTR; uint32_t savePIPEACONF; uint32_t savePIPEBCONF; - uint32_t savePIPEASRC; - uint32_t savePIPEBSRC; uint32_t saveFPA0; uint32_t saveFPA1; uint32_t saveDPLL_A; uint32_t saveDPLL_A_MD; - uint32_t saveHTOTAL_A; - uint32_t saveHBLANK_A; - uint32_t saveHSYNC_A; - uint32_t saveVTOTAL_A; - uint32_t saveVBLANK_A; - uint32_t saveVSYNC_A; - uint32_t saveDSPASTRIDE; - uint32_t saveDSPASIZE; - uint32_t saveDSPAPOS; uint32_t saveDSPABASE; - uint32_t saveDSPASURF; - uint32_t saveDSPASTATUS; uint32_t saveFPB0; uint32_t saveFPB1; uint32_t saveDPLL_B; uint32_t saveDPLL_B_MD; - uint32_t saveHTOTAL_B; - uint32_t saveHBLANK_B; - uint32_t saveHSYNC_B; - uint32_t saveVTOTAL_B; - uint32_t saveVBLANK_B; - uint32_t saveVSYNC_B; - uint32_t saveDSPBSTRIDE; - uint32_t saveDSPBSIZE; - uint32_t saveDSPBPOS; uint32_t saveDSPBBASE; - uint32_t saveDSPBSURF; - uint32_t saveDSPBSTATUS; uint32_t saveVCLK_DIVISOR_VGA0; uint32_t saveVCLK_DIVISOR_VGA1; uint32_t saveVCLK_POST_DIV; @@ -751,8 +745,6 @@ struct drm_psb_private { uint32_t saveBLC_PWM_CTL; uint32_t saveCLOCKGATING; uint32_t saveDSPARB; - uint32_t saveDSPATILEOFF; - uint32_t saveDSPBTILEOFF; uint32_t saveDSPAADDR; uint32_t saveDSPBADDR; uint32_t savePFIT_AUTO_RATIOS; @@ -764,8 +756,6 @@ struct drm_psb_private { uint32_t saveVBT; uint32_t saveBCLRPAT_A; uint32_t saveBCLRPAT_B; - uint32_t saveDSPALINOFF; - uint32_t saveDSPBLINOFF; uint32_t savePERF_MODE; uint32_t saveDSPFW1; uint32_t saveDSPFW2; @@ -804,20 +794,6 @@ struct drm_psb_private { uint32_t saveHDMIB_CONTROL; uint32_t saveDSPCCNTR; uint32_t savePIPECCONF; - uint32_t savePIPECSRC; - uint32_t saveHTOTAL_C; - uint32_t saveHBLANK_C; - uint32_t saveHSYNC_C; - uint32_t saveVTOTAL_C; - uint32_t saveVBLANK_C; - uint32_t saveVSYNC_C; - uint32_t saveDSPCSTRIDE; - uint32_t saveDSPCSIZE; - uint32_t saveDSPCPOS; - uint32_t saveDSPCSURF; - uint32_t saveDSPCSTATUS; - uint32_t saveDSPCLINOFF; - uint32_t saveDSPCTILEOFF; uint32_t saveDSPCCURSOR_CTRL; uint32_t saveDSPCCURSOR_BASE; uint32_t saveDSPCCURSOR_POS; diff --git a/drivers/staging/mrst/drv/psb_powermgmt.c b/drivers/staging/mrst/drv/psb_powermgmt.c index f340f80..8fb8dda 100644 --- a/drivers/staging/mrst/drv/psb_powermgmt.c +++ b/drivers/staging/mrst/drv/psb_powermgmt.c @@ -472,50 +472,23 @@ void ospm_power_uninit(struct drm_device *drm_dev) static int mdfld_save_display_registers(struct drm_device *dev, int pipe) { struct drm_psb_private *dev_priv = dev->dev_private; + struct psb_pipe_regs *pr = &dev_priv->pipe_regs[pipe]; int i; /* regester */ u32 dpll_reg = MRST_DPLL_A; u32 fp_reg = MRST_FPA0; u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); - u32 htot_reg = PSB_HTOTAL(PSB_PIPE_A); - u32 hblank_reg = PSB_HBLANK(PSB_PIPE_A); - u32 hsync_reg = PSB_HSYNC(PSB_PIPE_A); - u32 vtot_reg = PSB_VTOTAL(PSB_PIPE_A); - u32 vblank_reg = PSB_VBLANK(PSB_PIPE_A); - u32 vsync_reg = PSB_VSYNC(PSB_PIPE_A); - u32 pipesrc_reg = PSB_PIPESRC(PSB_PIPE_A); - u32 dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_A); - u32 dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A); - u32 dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_A); - u32 dspsize_reg = PSB_DSPSIZE(PSB_PIPE_A); - u32 dsppos_reg = PSB_DSPPOS(PSB_PIPE_A); - u32 dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A); u32 mipi_reg = MIPI; u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); - u32 dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_A); u32 palette_reg = PALETTE_A; /* pointer to values */ u32 *dpll_val = &dev_priv->saveDPLL_A; u32 *fp_val = &dev_priv->saveFPA0; u32 *pipeconf_val = &dev_priv->savePIPEACONF; - u32 *htot_val = &dev_priv->saveHTOTAL_A; - u32 *hblank_val = &dev_priv->saveHBLANK_A; - u32 *hsync_val = &dev_priv->saveHSYNC_A; - u32 *vtot_val = &dev_priv->saveVTOTAL_A; - u32 *vblank_val = &dev_priv->saveVBLANK_A; - u32 *vsync_val = &dev_priv->saveVSYNC_A; - u32 *pipesrc_val = &dev_priv->savePIPEASRC; - u32 *dspstride_val = &dev_priv->saveDSPASTRIDE; - u32 *dsplinoff_val = &dev_priv->saveDSPALINOFF; - u32 *dsptileoff_val = &dev_priv->saveDSPATILEOFF; - u32 *dspsize_val = &dev_priv->saveDSPASIZE; - u32 *dsppos_val = &dev_priv->saveDSPAPOS; - u32 *dspsurf_val = &dev_priv->saveDSPASURF; u32 *mipi_val = &dev_priv->saveMIPI; u32 *dspcntr_val = &dev_priv->saveDSPACNTR; - u32 *dspstatus_val = &dev_priv->saveDSPASTATUS; u32 *palette_val = dev_priv->save_palette_a; PSB_DEBUG_ENTRY("\n"); @@ -527,83 +500,27 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe) dpll_reg = MDFLD_DPLL_B; fp_reg = MDFLD_DPLL_DIV0; pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B); - htot_reg = PSB_HTOTAL(PSB_PIPE_B); - hblank_reg = PSB_HBLANK(PSB_PIPE_B); - hsync_reg = PSB_HSYNC(PSB_PIPE_B); - vtot_reg = PSB_VTOTAL(PSB_PIPE_B); - vblank_reg = PSB_VBLANK(PSB_PIPE_B); - vsync_reg = PSB_VSYNC(PSB_PIPE_B); - pipesrc_reg = PSB_PIPESRC(PSB_PIPE_B); - dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_B); - dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_B); - dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_B); - dspsize_reg = PSB_DSPSIZE(PSB_PIPE_B); - dsppos_reg = PSB_DSPPOS(PSB_PIPE_B); - dspsurf_reg = PSB_DSPSURF(PSB_PIPE_B); dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B); - dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_B); palette_reg = PALETTE_B; /* values */ dpll_val = &dev_priv->saveDPLL_B; fp_val = &dev_priv->saveFPB0; pipeconf_val = &dev_priv->savePIPEBCONF; - htot_val = &dev_priv->saveHTOTAL_B; - hblank_val = &dev_priv->saveHBLANK_B; - hsync_val = &dev_priv->saveHSYNC_B; - vtot_val = &dev_priv->saveVTOTAL_B; - vblank_val = &dev_priv->saveVBLANK_B; - vsync_val = &dev_priv->saveVSYNC_B; - pipesrc_val = &dev_priv->savePIPEBSRC; - dspstride_val = &dev_priv->saveDSPBSTRIDE; - dsplinoff_val = &dev_priv->saveDSPBLINOFF; - dsptileoff_val = &dev_priv->saveDSPBTILEOFF; - dspsize_val = &dev_priv->saveDSPBSIZE; - dsppos_val = &dev_priv->saveDSPBPOS; - dspsurf_val = &dev_priv->saveDSPBSURF; dspcntr_val = &dev_priv->saveDSPBCNTR; - dspstatus_val = &dev_priv->saveDSPBSTATUS; palette_val = dev_priv->save_palette_b; break; case 2: /* regester */ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); - htot_reg = PSB_HTOTAL(PSB_PIPE_C); - hblank_reg = PSB_HBLANK(PSB_PIPE_C); - hsync_reg = PSB_HSYNC(PSB_PIPE_C); - vtot_reg = PSB_VTOTAL(PSB_PIPE_C); - vblank_reg = PSB_VBLANK(PSB_PIPE_C); - vsync_reg = PSB_VSYNC(PSB_PIPE_C); - pipesrc_reg = PSB_PIPESRC(PSB_PIPE_C); - dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_C); - dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_C); - dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_C); - dspsize_reg = PSB_DSPSIZE(PSB_PIPE_C); - dsppos_reg = PSB_DSPPOS(PSB_PIPE_C); - dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C); mipi_reg = MIPI_C; dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C); - dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_C); palette_reg = PALETTE_C; /* pointer to values */ pipeconf_val = &dev_priv->savePIPECCONF; - htot_val = &dev_priv->saveHTOTAL_C; - hblank_val = &dev_priv->saveHBLANK_C; - hsync_val = &dev_priv->saveHSYNC_C; - vtot_val = &dev_priv->saveVTOTAL_C; - vblank_val = &dev_priv->saveVBLANK_C; - vsync_val = &dev_priv->saveVSYNC_C; - pipesrc_val = &dev_priv->savePIPECSRC; - dspstride_val = &dev_priv->saveDSPCSTRIDE; - dsplinoff_val = &dev_priv->saveDSPCLINOFF; - dsptileoff_val = &dev_priv->saveDSPCTILEOFF; - dspsize_val = &dev_priv->saveDSPCSIZE; - dsppos_val = &dev_priv->saveDSPCPOS; - dspsurf_val = &dev_priv->saveDSPCSURF; mipi_val = &dev_priv->saveMIPI_C; dspcntr_val = &dev_priv->saveDSPCCNTR; - dspstatus_val = &dev_priv->saveDSPCSTATUS; palette_val = dev_priv->save_palette_c; break; default: @@ -615,21 +532,22 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe) *dpll_val = PSB_RVDC32(dpll_reg); *fp_val = PSB_RVDC32(fp_reg); *pipeconf_val = PSB_RVDC32(pipeconf_reg); - *htot_val = PSB_RVDC32(htot_reg); - *hblank_val = PSB_RVDC32(hblank_reg); - *hsync_val = PSB_RVDC32(hsync_reg); - *vtot_val = PSB_RVDC32(vtot_reg); - *vblank_val = PSB_RVDC32(vblank_reg); - *vsync_val = PSB_RVDC32(vsync_reg); - *pipesrc_val = PSB_RVDC32(pipesrc_reg); - *dspstride_val = PSB_RVDC32(dspstride_reg); - *dsplinoff_val = PSB_RVDC32(dsplinoff_reg); - *dsptileoff_val = PSB_RVDC32(dsptileoff_reg); - *dspsize_val = PSB_RVDC32(dspsize_reg); - *dsppos_val = PSB_RVDC32(dsppos_reg); - *dspsurf_val = PSB_RVDC32(dspsurf_reg); *dspcntr_val = PSB_RVDC32(dspcntr_reg); - *dspstatus_val = PSB_RVDC32(dspstatus_reg); + + pr->htotal = PSB_RVDC32(PSB_HTOTAL(pipe)); + pr->hblank = PSB_RVDC32(PSB_HBLANK(pipe)); + pr->hsync = PSB_RVDC32(PSB_HSYNC(pipe)); + pr->vtotal = PSB_RVDC32(PSB_VTOTAL(pipe)); + pr->vblank = PSB_RVDC32(PSB_VBLANK(pipe)); + pr->vsync = PSB_RVDC32(PSB_VSYNC(pipe)); + pr->src = PSB_RVDC32(PSB_PIPESRC(pipe)); + pr->dsp_stride = PSB_RVDC32(PSB_DSPSTRIDE(pipe)); + pr->dsp_line_offs = PSB_RVDC32(PSB_DSPLINOFF(pipe)); + pr->dsp_tile_offs = PSB_RVDC32(PSB_DSPTILEOFF(pipe)); + pr->dsp_size = PSB_RVDC32(PSB_DSPSIZE(pipe)); + pr->dsp_pos = PSB_RVDC32(PSB_DSPPOS(pipe)); + pr->dsp_surf = PSB_RVDC32(PSB_DSPSURF(pipe)); + pr->dsp_status = PSB_RVDC32(PSB_PIPESTAT(pipe)); /*save palette (gamma) */ for (i = 0; i < 256; i++) @@ -690,6 +608,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) u32 temp = 0; u32 device_ready_reg = DEVICE_READY_REG; struct drm_psb_private *dev_priv = dev->dev_private; + struct psb_pipe_regs *pr = &dev_priv->pipe_regs[pipe]; struct mdfld_dsi_dbi_output * dsi_output = dev_priv->dbi_output; struct mdfld_dsi_config * dsi_config = NULL; u32 i = 0; @@ -700,20 +619,6 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) u32 dpll_reg = MRST_DPLL_A; u32 fp_reg = MRST_FPA0; u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A); - u32 htot_reg = PSB_HTOTAL(PSB_PIPE_A); - u32 hblank_reg = PSB_HBLANK(PSB_PIPE_A); - u32 hsync_reg = PSB_HSYNC(PSB_PIPE_A); - u32 vtot_reg = PSB_VTOTAL(PSB_PIPE_A); - u32 vblank_reg = PSB_VBLANK(PSB_PIPE_A); - u32 vsync_reg = PSB_VSYNC(PSB_PIPE_A); - u32 pipesrc_reg = PSB_PIPESRC(PSB_PIPE_A); - u32 dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_A); - u32 dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A); - u32 dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_A); - u32 dspsize_reg = PSB_DSPSIZE(PSB_PIPE_A); - u32 dsppos_reg = PSB_DSPPOS(PSB_PIPE_A); - u32 dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A); - u32 dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_A); u32 mipi_reg = MIPI; u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A); u32 palette_reg = PALETTE_A; @@ -722,20 +627,6 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) u32 dpll_val = dev_priv->saveDPLL_A & ~DPLL_VCO_ENABLE; u32 fp_val = dev_priv->saveFPA0; u32 pipeconf_val = dev_priv->savePIPEACONF; - u32 htot_val = dev_priv->saveHTOTAL_A; - u32 hblank_val = dev_priv->saveHBLANK_A; - u32 hsync_val = dev_priv->saveHSYNC_A; - u32 vtot_val = dev_priv->saveVTOTAL_A; - u32 vblank_val = dev_priv->saveVBLANK_A; - u32 vsync_val = dev_priv->saveVSYNC_A; - u32 pipesrc_val = dev_priv->savePIPEASRC; - u32 dspstride_val = dev_priv->saveDSPASTRIDE; - u32 dsplinoff_val = dev_priv->saveDSPALINOFF; - u32 dsptileoff_val = dev_priv->saveDSPATILEOFF; - u32 dspsize_val = dev_priv->saveDSPASIZE; - u32 dsppos_val = dev_priv->saveDSPAPOS; - u32 dspsurf_val = dev_priv->saveDSPASURF; - u32 dspstatus_val = dev_priv->saveDSPASTATUS; u32 mipi_val = dev_priv->saveMIPI; u32 dspcntr_val = dev_priv->saveDSPACNTR; u32 *palette_val = dev_priv->save_palette_a; @@ -750,42 +641,14 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) dpll_reg = MDFLD_DPLL_B; fp_reg = MDFLD_DPLL_DIV0; pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B); - htot_reg = PSB_HTOTAL(PSB_PIPE_B); - hblank_reg = PSB_HBLANK(PSB_PIPE_B); - hsync_reg = PSB_HSYNC(PSB_PIPE_B); - vtot_reg = PSB_VTOTAL(PSB_PIPE_B); - vblank_reg = PSB_VBLANK(PSB_PIPE_B); - vsync_reg = PSB_VSYNC(PSB_PIPE_B); - pipesrc_reg = PSB_PIPESRC(PSB_PIPE_B); - dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_B); - dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_B); - dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_B); - dspsize_reg = PSB_DSPSIZE(PSB_PIPE_B); - dsppos_reg = PSB_DSPPOS(PSB_PIPE_B); - dspsurf_reg = PSB_DSPSURF(PSB_PIPE_B); dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B); - dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_B); palette_reg = PALETTE_B; /* values */ dpll_val = dev_priv->saveDPLL_B & ~DPLL_VCO_ENABLE; fp_val = dev_priv->saveFPB0; pipeconf_val = dev_priv->savePIPEBCONF; - htot_val = dev_priv->saveHTOTAL_B; - hblank_val = dev_priv->saveHBLANK_B; - hsync_val = dev_priv->saveHSYNC_B; - vtot_val = dev_priv->saveVTOTAL_B; - vblank_val = dev_priv->saveVBLANK_B; - vsync_val = dev_priv->saveVSYNC_B; - pipesrc_val = dev_priv->savePIPEBSRC; - dspstride_val = dev_priv->saveDSPBSTRIDE; - dsplinoff_val = dev_priv->saveDSPBLINOFF; - dsptileoff_val = dev_priv->saveDSPBTILEOFF; - dspsize_val = dev_priv->saveDSPBSIZE; - dsppos_val = dev_priv->saveDSPBPOS; - dspsurf_val = dev_priv->saveDSPBSURF; dspcntr_val = dev_priv->saveDSPBCNTR; - dspstatus_val = dev_priv->saveDSPBSTATUS; palette_val = dev_priv->save_palette_b; break; case 2: @@ -793,42 +656,14 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) /* regester */ pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C); - htot_reg = PSB_HTOTAL(PSB_PIPE_C); - hblank_reg = PSB_HBLANK(PSB_PIPE_C); - hsync_reg = PSB_HSYNC(PSB_PIPE_C); - vtot_reg = PSB_VTOTAL(PSB_PIPE_C); - vblank_reg = PSB_VBLANK(PSB_PIPE_C); - vsync_reg = PSB_VSYNC(PSB_PIPE_C); - pipesrc_reg = PSB_PIPESRC(PSB_PIPE_C); - dspstride_reg = PSB_DSPSTRIDE(PSB_PIPE_C); - dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_C); - dsptileoff_reg = PSB_DSPTILEOFF(PSB_PIPE_C); - dspsize_reg = PSB_DSPSIZE(PSB_PIPE_C); - dsppos_reg = PSB_DSPPOS(PSB_PIPE_C); - dspsurf_reg = PSB_DSPSURF(PSB_PIPE_C); mipi_reg = MIPI_C; dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C); - dspstatus_reg = PSB_PIPESTAT(PSB_PIPE_C); palette_reg = PALETTE_C; /* values */ pipeconf_val = dev_priv->savePIPECCONF; - htot_val = dev_priv->saveHTOTAL_C; - hblank_val = dev_priv->saveHBLANK_C; - hsync_val = dev_priv->saveHSYNC_C; - vtot_val = dev_priv->saveVTOTAL_C; - vblank_val = dev_priv->saveVBLANK_C; - vsync_val = dev_priv->saveVSYNC_C; - pipesrc_val = dev_priv->savePIPECSRC; - dspstride_val = dev_priv->saveDSPCSTRIDE; - dsplinoff_val = dev_priv->saveDSPCLINOFF; - dsptileoff_val = dev_priv->saveDSPCTILEOFF; - dspsize_val = dev_priv->saveDSPCSIZE; - dsppos_val = dev_priv->saveDSPCPOS; - dspsurf_val = dev_priv->saveDSPCSURF; mipi_val = dev_priv->saveMIPI_C; dspcntr_val = dev_priv->saveDSPCCNTR; - dspstatus_val = dev_priv->saveDSPCSTATUS; palette_val = dev_priv->save_palette_c; dsi_config = dev_priv->dsi_configs[1]; @@ -881,23 +716,21 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) } } } - /* Restore mode */ - PSB_WVDC32(htot_val, htot_reg); - PSB_WVDC32(hblank_val, hblank_reg); - PSB_WVDC32(hsync_val, hsync_reg); - PSB_WVDC32(vtot_val, vtot_reg); - PSB_WVDC32(vblank_val, vblank_reg); - PSB_WVDC32(vsync_val, vsync_reg); - PSB_WVDC32(pipesrc_val, pipesrc_reg); - PSB_WVDC32(dspstatus_val, dspstatus_reg); - - /*set up the plane*/ - PSB_WVDC32(dspstride_val, dspstride_reg); - PSB_WVDC32(dsplinoff_val, dsplinoff_reg); - PSB_WVDC32(dsptileoff_val, dsptileoff_reg); - PSB_WVDC32(dspsize_val, dspsize_reg); - PSB_WVDC32(dsppos_val, dsppos_reg); - PSB_WVDC32(dspsurf_val, dspsurf_reg); + + PSB_WVDC32(pr->htotal, PSB_HTOTAL(pipe)); + PSB_WVDC32(pr->hblank, PSB_HBLANK(pipe)); + PSB_WVDC32(pr->hsync, PSB_HSYNC(pipe)); + PSB_WVDC32(pr->vtotal, PSB_VTOTAL(pipe)); + PSB_WVDC32(pr->vblank, PSB_VBLANK(pipe)); + PSB_WVDC32(pr->vsync, PSB_VSYNC(pipe)); + PSB_WVDC32(pr->src, PSB_PIPESRC(pipe)); + PSB_WVDC32(pr->dsp_status, PSB_PIPESTAT(pipe)); + PSB_WVDC32(pr->dsp_stride, PSB_DSPSTRIDE(pipe)); + PSB_WVDC32(pr->dsp_line_offs, PSB_DSPLINOFF(pipe)); + PSB_WVDC32(pr->dsp_tile_offs, PSB_DSPTILEOFF(pipe)); + PSB_WVDC32(pr->dsp_size, PSB_DSPSIZE(pipe)); + PSB_WVDC32(pr->dsp_pos, PSB_DSPPOS(pipe)); + PSB_WVDC32(pr->dsp_surf, PSB_DSPSURF(pipe)); if (pipe == 1) { /* restore palette (gamma) */ -- 2.7.4