From 2c83809fa8131f33d75bf1956376ad07e25d7169 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Amaury=20S=C3=A9chet?= Date: Wed, 14 Jun 2023 16:27:58 +0000 Subject: [PATCH] [NFC] Automatically generate arm64-dagcombiner-dead-indexed-load.ll --- .../CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll b/llvm/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll index efe1e20..f504aeb 100644 --- a/llvm/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll +++ b/llvm/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc -mcpu=cyclone < %s | FileCheck %s target datalayout = "e-i64:64-n32:64-S128" target triple = "arm64-apple-ios" @@ -10,12 +11,11 @@ target triple = "arm64-apple-ios" ; This is a read-modify-write of some bifields combined into an i48. It gets ; legalized into i32 and i16 accesses. Only a single store of zero to the low ; i32 part should be live. - -; CHECK-LABEL: test: -; CHECK-NOT: ldr -; CHECK: str wzr -; CHECK-NOT: str define void @test(ptr nocapture %su) { +; CHECK-LABEL: test: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: str wzr, [x0, #96] +; CHECK-NEXT: ret entry: %r1 = getelementptr inbounds %"struct.SU", ptr %su, i64 1, i32 5 %r3 = load i48, ptr %r1, align 8 -- 2.7.4