From 2c7d52a5407ad7145629a8d089b3aa59547a158f Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Fri, 9 Dec 2016 19:08:15 +0000 Subject: [PATCH] Move .mir tests to appropriate directories test/CodeGen/MIR should contain tests that intent to test the MIR printing or parsing. Tests that test something else should be in test/CodeGen/TargetName even when they are written in .mir. As a rule of thumb, only tests using "llc -run-pass none" should be in test/CodeGen/MIR. llvm-svn: 289254 --- llvm/test/CodeGen/{MIR => }/AArch64/ldst-opt-zr-clobber.mir | 0 llvm/test/CodeGen/{MIR => }/AArch64/machine-dead-copy.mir | 0 llvm/test/CodeGen/{MIR => }/AArch64/machine-scheduler.mir | 0 llvm/test/CodeGen/{MIR => }/AArch64/machine-sink-zr.mir | 0 llvm/test/CodeGen/{MIR => }/AMDGPU/coalescer-subreg-join.mir | 0 llvm/test/CodeGen/{MIR => }/AMDGPU/detect-dead-lanes.mir | 0 llvm/test/CodeGen/{MIR => }/AMDGPU/insert-waits-exp.mir | 0 llvm/test/CodeGen/{MIR => }/AMDGPU/inserted-wait-states.mir | 0 llvm/test/CodeGen/{MIR => }/AMDGPU/invert-br-undef-vcc.mir | 0 llvm/test/CodeGen/{MIR => }/AMDGPU/liveness.mir | 0 llvm/test/CodeGen/{MIR => }/AMDGPU/movrels-bug.mir | 0 llvm/test/CodeGen/{MIR => }/AMDGPU/optimize-if-exec-masking.mir | 0 llvm/test/CodeGen/{MIR => }/AMDGPU/rename-independent-subregs.mir | 0 llvm/test/CodeGen/{MIR => }/AMDGPU/scalar-store-cache-flush.mir | 0 llvm/test/CodeGen/{MIR => }/AMDGPU/si-fix-sgpr-copies.mir | 0 llvm/test/CodeGen/{MIR => }/AMDGPU/subreg-intervals.mir | 0 llvm/test/CodeGen/{MIR => }/AMDGPU/vccz-corrupt-bug-workaround.mir | 0 llvm/test/CodeGen/{MIR => }/AMDGPU/waitcnt.mir | 0 llvm/test/CodeGen/{MIR => }/ARM/imm-peephole-arm.mir | 0 llvm/test/CodeGen/{MIR => }/ARM/imm-peephole-thumb.mir | 0 llvm/test/CodeGen/{MIR => }/Hexagon/anti-dep-partial.mir | 0 llvm/test/CodeGen/{MIR => }/Lanai/peephole-compare.mir | 0 llvm/test/CodeGen/MIR/Lanai/lit.local.cfg | 2 -- 23 files changed, 2 deletions(-) rename llvm/test/CodeGen/{MIR => }/AArch64/ldst-opt-zr-clobber.mir (100%) rename llvm/test/CodeGen/{MIR => }/AArch64/machine-dead-copy.mir (100%) rename llvm/test/CodeGen/{MIR => }/AArch64/machine-scheduler.mir (100%) rename llvm/test/CodeGen/{MIR => }/AArch64/machine-sink-zr.mir (100%) rename llvm/test/CodeGen/{MIR => }/AMDGPU/coalescer-subreg-join.mir (100%) rename llvm/test/CodeGen/{MIR => }/AMDGPU/detect-dead-lanes.mir (100%) rename llvm/test/CodeGen/{MIR => }/AMDGPU/insert-waits-exp.mir (100%) rename llvm/test/CodeGen/{MIR => }/AMDGPU/inserted-wait-states.mir (100%) rename llvm/test/CodeGen/{MIR => }/AMDGPU/invert-br-undef-vcc.mir (100%) rename llvm/test/CodeGen/{MIR => }/AMDGPU/liveness.mir (100%) rename llvm/test/CodeGen/{MIR => }/AMDGPU/movrels-bug.mir (100%) rename llvm/test/CodeGen/{MIR => }/AMDGPU/optimize-if-exec-masking.mir (100%) rename llvm/test/CodeGen/{MIR => }/AMDGPU/rename-independent-subregs.mir (100%) rename llvm/test/CodeGen/{MIR => }/AMDGPU/scalar-store-cache-flush.mir (100%) rename llvm/test/CodeGen/{MIR => }/AMDGPU/si-fix-sgpr-copies.mir (100%) rename llvm/test/CodeGen/{MIR => }/AMDGPU/subreg-intervals.mir (100%) rename llvm/test/CodeGen/{MIR => }/AMDGPU/vccz-corrupt-bug-workaround.mir (100%) rename llvm/test/CodeGen/{MIR => }/AMDGPU/waitcnt.mir (100%) rename llvm/test/CodeGen/{MIR => }/ARM/imm-peephole-arm.mir (100%) rename llvm/test/CodeGen/{MIR => }/ARM/imm-peephole-thumb.mir (100%) rename llvm/test/CodeGen/{MIR => }/Hexagon/anti-dep-partial.mir (100%) rename llvm/test/CodeGen/{MIR => }/Lanai/peephole-compare.mir (100%) delete mode 100644 llvm/test/CodeGen/MIR/Lanai/lit.local.cfg diff --git a/llvm/test/CodeGen/MIR/AArch64/ldst-opt-zr-clobber.mir b/llvm/test/CodeGen/AArch64/ldst-opt-zr-clobber.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AArch64/ldst-opt-zr-clobber.mir rename to llvm/test/CodeGen/AArch64/ldst-opt-zr-clobber.mir diff --git a/llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir b/llvm/test/CodeGen/AArch64/machine-dead-copy.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir rename to llvm/test/CodeGen/AArch64/machine-dead-copy.mir diff --git a/llvm/test/CodeGen/MIR/AArch64/machine-scheduler.mir b/llvm/test/CodeGen/AArch64/machine-scheduler.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AArch64/machine-scheduler.mir rename to llvm/test/CodeGen/AArch64/machine-scheduler.mir diff --git a/llvm/test/CodeGen/MIR/AArch64/machine-sink-zr.mir b/llvm/test/CodeGen/AArch64/machine-sink-zr.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AArch64/machine-sink-zr.mir rename to llvm/test/CodeGen/AArch64/machine-sink-zr.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/coalescer-subreg-join.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AMDGPU/coalescer-subreg-join.mir rename to llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/detect-dead-lanes.mir b/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AMDGPU/detect-dead-lanes.mir rename to llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/insert-waits-exp.mir b/llvm/test/CodeGen/AMDGPU/insert-waits-exp.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AMDGPU/insert-waits-exp.mir rename to llvm/test/CodeGen/AMDGPU/insert-waits-exp.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/inserted-wait-states.mir b/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AMDGPU/inserted-wait-states.mir rename to llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invert-br-undef-vcc.mir b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AMDGPU/invert-br-undef-vcc.mir rename to llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/liveness.mir b/llvm/test/CodeGen/AMDGPU/liveness.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AMDGPU/liveness.mir rename to llvm/test/CodeGen/AMDGPU/liveness.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/movrels-bug.mir b/llvm/test/CodeGen/AMDGPU/movrels-bug.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AMDGPU/movrels-bug.mir rename to llvm/test/CodeGen/AMDGPU/movrels-bug.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/optimize-if-exec-masking.mir b/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AMDGPU/optimize-if-exec-masking.mir rename to llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/rename-independent-subregs.mir b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AMDGPU/rename-independent-subregs.mir rename to llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/scalar-store-cache-flush.mir b/llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AMDGPU/scalar-store-cache-flush.mir rename to llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/si-fix-sgpr-copies.mir b/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AMDGPU/si-fix-sgpr-copies.mir rename to llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/subreg-intervals.mir b/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AMDGPU/subreg-intervals.mir rename to llvm/test/CodeGen/AMDGPU/subreg-intervals.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/vccz-corrupt-bug-workaround.mir b/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AMDGPU/vccz-corrupt-bug-workaround.mir rename to llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/waitcnt.mir b/llvm/test/CodeGen/AMDGPU/waitcnt.mir similarity index 100% rename from llvm/test/CodeGen/MIR/AMDGPU/waitcnt.mir rename to llvm/test/CodeGen/AMDGPU/waitcnt.mir diff --git a/llvm/test/CodeGen/MIR/ARM/imm-peephole-arm.mir b/llvm/test/CodeGen/ARM/imm-peephole-arm.mir similarity index 100% rename from llvm/test/CodeGen/MIR/ARM/imm-peephole-arm.mir rename to llvm/test/CodeGen/ARM/imm-peephole-arm.mir diff --git a/llvm/test/CodeGen/MIR/ARM/imm-peephole-thumb.mir b/llvm/test/CodeGen/ARM/imm-peephole-thumb.mir similarity index 100% rename from llvm/test/CodeGen/MIR/ARM/imm-peephole-thumb.mir rename to llvm/test/CodeGen/ARM/imm-peephole-thumb.mir diff --git a/llvm/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir b/llvm/test/CodeGen/Hexagon/anti-dep-partial.mir similarity index 100% rename from llvm/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir rename to llvm/test/CodeGen/Hexagon/anti-dep-partial.mir diff --git a/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir b/llvm/test/CodeGen/Lanai/peephole-compare.mir similarity index 100% rename from llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir rename to llvm/test/CodeGen/Lanai/peephole-compare.mir diff --git a/llvm/test/CodeGen/MIR/Lanai/lit.local.cfg b/llvm/test/CodeGen/MIR/Lanai/lit.local.cfg deleted file mode 100644 index f1b8b4f..0000000 --- a/llvm/test/CodeGen/MIR/Lanai/lit.local.cfg +++ /dev/null @@ -1,2 +0,0 @@ -if not 'Lanai' in config.root.targets: - config.unsupported = True -- 2.7.4