From 2c4ba3e9d36e9d66ece0cb48156415b65888cf95 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Fri, 5 Nov 2021 09:14:32 -0700 Subject: [PATCH] [Target] Use make_early_inc_range (NFC) --- llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp | 9 ++------- llvm/lib/Target/AVR/AVRFrameLowering.cpp | 16 +++++++--------- llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp | 12 +++++------- llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp | 10 +++------- llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 13 +++---------- llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp | 7 ++----- llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp | 4 +--- llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp | 4 +--- llvm/lib/Target/PowerPC/PPCVSXCopy.cpp | 5 +---- llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp | 4 +--- llvm/lib/Target/X86/X86ISelLowering.cpp | 13 +++++-------- llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp | 9 ++++----- llvm/lib/Target/X86/X86LowerAMXType.cpp | 4 +--- llvm/lib/Target/X86/X86LowerTileCopy.cpp | 4 +--- llvm/lib/Target/X86/X86OptimizeLEAs.cpp | 5 ++--- 15 files changed, 39 insertions(+), 80 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp index 38548ea..6f63f68 100644 --- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp +++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp @@ -1029,11 +1029,8 @@ void SIWholeQuadMode::lowerBlock(MachineBasicBlock &MBB) { SmallVector SplitPoints; char State = BI.InitialState; - auto II = MBB.getFirstNonPHI(), IE = MBB.end(); - while (II != IE) { - auto Next = std::next(II); - MachineInstr &MI = *II; - + for (MachineInstr &MI : llvm::make_early_inc_range( + llvm::make_range(MBB.getFirstNonPHI(), MBB.end()))) { if (StateTransition.count(&MI)) State = StateTransition[&MI]; @@ -1051,8 +1048,6 @@ void SIWholeQuadMode::lowerBlock(MachineBasicBlock &MBB) { } if (SplitPoint) SplitPoints.push_back(SplitPoint); - - II = Next; } // Perform splitting after instruction scan to simplify iteration. diff --git a/llvm/lib/Target/AVR/AVRFrameLowering.cpp b/llvm/lib/Target/AVR/AVRFrameLowering.cpp index a4bde54..672611e 100644 --- a/llvm/lib/Target/AVR/AVRFrameLowering.cpp +++ b/llvm/lib/Target/AVR/AVRFrameLowering.cpp @@ -303,16 +303,16 @@ static void fixStackStores(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const TargetInstrInfo &TII, Register FP) { // Iterate through the BB until we hit a call instruction or we reach the end. - for (auto I = MI, E = MBB.end(); I != E && !I->isCall();) { - MachineBasicBlock::iterator NextMI = std::next(I); - MachineInstr &MI = *I; - unsigned Opcode = I->getOpcode(); + for (MachineInstr &MI : + llvm::make_early_inc_range(llvm::make_range(MI, MBB.end()))) { + if (MI.isCall()) + break; + + unsigned Opcode = MI.getOpcode(); // Only care of pseudo store instructions where SP is the base pointer. - if (Opcode != AVR::STDSPQRr && Opcode != AVR::STDWSPQRr) { - I = NextMI; + if (Opcode != AVR::STDSPQRr && Opcode != AVR::STDWSPQRr) continue; - } assert(MI.getOperand(0).getReg() == AVR::SP && "Invalid register, should be SP!"); @@ -324,8 +324,6 @@ static void fixStackStores(MachineBasicBlock &MBB, MI.setDesc(TII.get(STOpc)); MI.getOperand(0).setReg(FP); - - I = NextMI; } } diff --git a/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp b/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp index ae1f5ea..7e829ea 100644 --- a/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp +++ b/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp @@ -97,15 +97,13 @@ void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI, // Go through all uses of %1 as in %1 = ADD_rr %2, %3 const MachineOperand Op0 = Inst->getOperand(0); - auto Begin = MRI->use_begin(Op0.getReg()), End = MRI->use_end(); - decltype(End) NextI; - for (auto I = Begin; I != End; I = NextI) { - NextI = std::next(I); + for (MachineOperand &MO : + llvm::make_early_inc_range(MRI->use_operands(Op0.getReg()))) { // The candidate needs to have a unique definition. - if (!MRI->getUniqueVRegDef(I->getReg())) + if (!MRI->getUniqueVRegDef(MO.getReg())) continue; - MachineInstr *DefInst = I->getParent(); + MachineInstr *DefInst = MO.getParent(); unsigned Opcode = DefInst->getOpcode(); unsigned COREOp; if (Opcode == BPF::LDB || Opcode == BPF::LDH || Opcode == BPF::LDW || @@ -131,7 +129,7 @@ void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI, Opcode == BPF::STD || Opcode == BPF::STB32 || Opcode == BPF::STH32 || Opcode == BPF::STW32) { const MachineOperand &Opnd = DefInst->getOperand(0); - if (Opnd.isReg() && Opnd.getReg() == I->getReg()) + if (Opnd.isReg() && Opnd.getReg() == MO.getReg()) continue; } diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp index 8dc26ba..7579a5e 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp @@ -1045,13 +1045,9 @@ bool MachineConstPropagator::rewrite(MachineFunction &MF) { // erase instructions during rewriting, so this needs to be delayed until // now. for (MachineBasicBlock &B : MF) { - MachineBasicBlock::iterator I = B.begin(), E = B.end(); - while (I != E) { - auto Next = std::next(I); - if (I->isBranch() && !InstrExec.count(&*I)) - B.erase(I); - I = Next; - } + for (MachineInstr &MI : llvm::make_early_inc_range(B)) + if (MI.isBranch() && !InstrExec.count(&MI)) + B.erase(&MI); } return Changed; } diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index cb73f43..1d32555 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -234,16 +234,9 @@ bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) { // dependence between Insn 0 and Insn 2. This can lead to incorrect // packetization for (MachineBasicBlock &MB : MF) { - auto End = MB.end(); - auto MI = MB.begin(); - while (MI != End) { - auto NextI = std::next(MI); - if (MI->isKill()) { - MB.erase(MI); - End = MB.end(); - } - MI = NextI; - } + for (MachineInstr &MI : llvm::make_early_inc_range(MB)) + if (MI.isKill()) + MB.erase(&MI); } // TinyCore with Duplexes: Translate to big-instructions. diff --git a/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp b/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp index efed44d..5a2c295 100644 --- a/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp +++ b/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp @@ -185,12 +185,9 @@ public: // nothing to do. if (MF.size() < 2) return Changed; - - // We can't use a range-based for loop due to clobbering the iterator. - for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E;) { - MachineBasicBlock &B = *I++; + + for (MachineBasicBlock &B : llvm::make_early_inc_range(MF)) Changed |= processBlock(B); - } return Changed; } diff --git a/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp b/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp index 3186d19..fbd487f 100644 --- a/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp +++ b/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp @@ -208,11 +208,9 @@ public: bool Changed = false; - for (MachineFunction::iterator I = MF.begin(); I != MF.end();) { - MachineBasicBlock &B = *I++; + for (MachineBasicBlock &B : llvm::make_early_inc_range(MF)) if (processBlock(B)) Changed = true; - } return Changed; } diff --git a/llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp b/llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp index 3811f88..8120975 100644 --- a/llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp +++ b/llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp @@ -131,11 +131,9 @@ public: bool runOnMachineFunction(MachineFunction &MF) override { bool Changed = false; - for (MachineFunction::iterator I = MF.begin(); I != MF.end();) { - MachineBasicBlock &B = *I++; + for (MachineBasicBlock &B : llvm::make_early_inc_range(MF)) if (processBlock(B)) Changed = true; - } return Changed; } diff --git a/llvm/lib/Target/PowerPC/PPCVSXCopy.cpp b/llvm/lib/Target/PowerPC/PPCVSXCopy.cpp index fd9bf96..7272e6e 100644 --- a/llvm/lib/Target/PowerPC/PPCVSXCopy.cpp +++ b/llvm/lib/Target/PowerPC/PPCVSXCopy.cpp @@ -148,11 +148,9 @@ public: bool Changed = false; - for (MachineFunction::iterator I = MF.begin(); I != MF.end();) { - MachineBasicBlock &B = *I++; + for (MachineBasicBlock &B : llvm::make_early_inc_range(MF)) if (processBlock(B)) Changed = true; - } return Changed; } @@ -169,4 +167,3 @@ INITIALIZE_PASS(PPCVSXCopy, DEBUG_TYPE, char PPCVSXCopy::ID = 0; FunctionPass* llvm::createPPCVSXCopyPass() { return new PPCVSXCopy(); } - diff --git a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp index de39c9c..0be35ad 100644 --- a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp +++ b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp @@ -361,11 +361,9 @@ public: if (DisableVSXFMAMutate) return Changed; - for (MachineFunction::iterator I = MF.begin(); I != MF.end();) { - MachineBasicBlock &B = *I++; + for (MachineBasicBlock &B : llvm::make_early_inc_range(MF)) if (processBlock(B)) Changed = true; - } return Changed; } diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 3d60ec9..9a80394 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -33838,14 +33838,11 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr &MI, } // Transfer any debug instructions inside the CMOV sequence to the sunk block. - auto DbgEnd = MachineBasicBlock::iterator(LastCMOV); - auto DbgIt = MachineBasicBlock::iterator(MI); - while (DbgIt != DbgEnd) { - auto Next = std::next(DbgIt); - if (DbgIt->isDebugInstr()) - SinkMBB->push_back(DbgIt->removeFromParent()); - DbgIt = Next; - } + auto DbgRange = llvm::make_range(MachineBasicBlock::iterator(MI), + MachineBasicBlock::iterator(LastCMOV)); + for (MachineInstr &MI : llvm::make_early_inc_range(DbgRange)) + if (MI.isDebugInstr()) + SinkMBB->push_back(MI.removeFromParent()); // Transfer the remainder of ThisMBB and its successor edges to SinkMBB. SinkMBB->splice(SinkMBB->end(), ThisMBB, diff --git a/llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp b/llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp index 248069f..08cf86b 100644 --- a/llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp +++ b/llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp @@ -498,8 +498,8 @@ X86LowerAMXIntrinsics::lowerTileDP(Instruction *TileDP) { Value *ResAMX = Builder.CreateBitCast(ResVec, Type::getX86_AMXTy(Builder.getContext())); // Delete TileDP intrinsic and do some clean-up. - for (auto UI = TileDP->use_begin(), UE = TileDP->use_end(); UI != UE;) { - Instruction *I = cast((UI++)->getUser()); + for (Use &U : llvm::make_early_inc_range(TileDP->uses())) { + Instruction *I = cast(U.getUser()); Value *Vec; if (match(I, m_BitCast(m_Value(Vec)))) { I->replaceAllUsesWith(ResVec); @@ -542,9 +542,8 @@ bool X86LowerAMXIntrinsics::lowerTileLoadStore(Instruction *TileLoadStore) { Value *ResAMX = Builder.CreateBitCast(ResVec, Type::getX86_AMXTy(Builder.getContext())); // Delete tileloadd6 intrinsic and do some clean-up - for (auto UI = TileLoadStore->use_begin(), UE = TileLoadStore->use_end(); - UI != UE;) { - Instruction *I = cast((UI++)->getUser()); + for (Use &U : llvm::make_early_inc_range(TileLoadStore->uses())) { + Instruction *I = cast(U.getUser()); Value *Vec; if (match(I, m_BitCast(m_Value(Vec)))) { I->replaceAllUsesWith(ResVec); diff --git a/llvm/lib/Target/X86/X86LowerAMXType.cpp b/llvm/lib/Target/X86/X86LowerAMXType.cpp index 719cd53..8e82119 100644 --- a/llvm/lib/Target/X86/X86LowerAMXType.cpp +++ b/llvm/lib/Target/X86/X86LowerAMXType.cpp @@ -302,9 +302,7 @@ bool X86LowerAMXType::visit() { Col2Row.clear(); for (BasicBlock *BB : post_order(&Func)) { - for (BasicBlock::reverse_iterator II = BB->rbegin(), IE = BB->rend(); - II != IE;) { - Instruction &Inst = *II++; + for (Instruction &Inst : llvm::make_early_inc_range(llvm::reverse(*BB))) { auto *Bitcast = dyn_cast(&Inst); if (!Bitcast) continue; diff --git a/llvm/lib/Target/X86/X86LowerTileCopy.cpp b/llvm/lib/Target/X86/X86LowerTileCopy.cpp index 03692d1..d6b4214 100644 --- a/llvm/lib/Target/X86/X86LowerTileCopy.cpp +++ b/llvm/lib/Target/X86/X86LowerTileCopy.cpp @@ -75,9 +75,7 @@ bool X86LowerTileCopy::runOnMachineFunction(MachineFunction &MF) { bool Changed = false; for (MachineBasicBlock &MBB : MF) { - for (MachineBasicBlock::iterator MII = MBB.begin(), MIE = MBB.end(); - MII != MIE;) { - MachineInstr &MI = *MII++; + for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) { if (!MI.isCopy()) continue; MachineOperand &DstMO = MI.getOperand(0); diff --git a/llvm/lib/Target/X86/X86OptimizeLEAs.cpp b/llvm/lib/Target/X86/X86OptimizeLEAs.cpp index 659fb63..6967a96 100644 --- a/llvm/lib/Target/X86/X86OptimizeLEAs.cpp +++ b/llvm/lib/Target/X86/X86OptimizeLEAs.cpp @@ -653,9 +653,8 @@ bool X86OptimizeLEAPass::removeRedundantLEAs(MemOpMap &LEAs) { // isReplaceable function. Register FirstVReg = First.getOperand(0).getReg(); Register LastVReg = Last.getOperand(0).getReg(); - for (auto UI = MRI->use_begin(LastVReg), UE = MRI->use_end(); - UI != UE;) { - MachineOperand &MO = *UI++; + for (MachineOperand &MO : + llvm::make_early_inc_range(MRI->use_operands(LastVReg))) { MachineInstr &MI = *MO.getParent(); if (MI.isDebugValue()) { -- 2.7.4