From 2bc06b7604d214807918dea810b56e0840aa7ba3 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Thu, 29 Jun 2023 22:00:53 +0100 Subject: [PATCH] arm64: dts: qcom: c630: add panel bridge 1p2 regulator The VCC and VCCA supplies of the DSI<->eDP bridge are derived from vreg_l2a_1p2 and controlled by a GPIO on the PMIC. Add the regulator here so Linux can control it. Signed-off-by: Caleb Connolly Link: https://lore.kernel.org/r/20230627-c630-uart-and-1p2-reg-v2-1-496b581935c1@linaro.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 21048ad..fbe1874 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -80,6 +80,22 @@ }; }; + sw_edp_1p2: edp-1p2-regulator { + compatible = "regulator-fixed"; + regulator-name = "sw_edp_1p2"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + pinctrl-0 = <&sw_edp_1p2_en>; + pinctrl-names = "default"; + + gpio = <&pm8998_gpios 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_l2a_1p2>; + }; + sn65dsi86_refclk: sn65dsi86-refclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -406,6 +422,8 @@ enable-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + vcca-supply = <&sw_edp_1p2>; + vcc-supply = <&sw_edp_1p2>; vpll-supply = <&vreg_l14a_1p88>; vccio-supply = <&vreg_l14a_1p88>; @@ -500,6 +518,16 @@ firmware-name = "qcom/sdm850/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/sdm850/LENOVO/81JL/qcdsp2850.mbn"; }; +&pm8998_gpios { + /* This pin is pulled down by a fixed resistor */ + sw_edp_1p2_en: pm8998-gpio9-state { + pins = "gpio9"; + function = "normal"; + bias-disable; + qcom,drive-strength = <0>; + }; +}; + &qup_i2c10_default { drive-strength = <2>; bias-disable; -- 2.7.4