From 2bad4a7177669787f3c7a8a3150c5e98e7c50b3e Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Tue, 30 Dec 2014 21:01:38 +0000 Subject: [PATCH] [Hexagon] Adding indexed store of immediates. llvm-svn: 225006 --- llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 18 ++-- llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td | 127 ++++++++++++++++++-------- llvm/test/MC/Disassembler/Hexagon/st.txt | 36 ++++++++ 3 files changed, 133 insertions(+), 48 deletions(-) diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 933a2d8..a741414 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -694,9 +694,9 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { case Hexagon::L2_loadrub_pi: return isInt<4>(MI->getOperand(3).getImm()); - case Hexagon::STrib_imm_V4: - case Hexagon::STrih_imm_V4: - case Hexagon::STriw_imm_V4: + case Hexagon::S4_storeirb_io: + case Hexagon::S4_storeirh_io: + case Hexagon::S4_storeiri_io: return (isUInt<6>(MI->getOperand(1).getImm()) && isInt<6>(MI->getOperand(2).getImm())); @@ -1420,8 +1420,8 @@ isConditionalStore (const MachineInstr* MI) const { switch (MI->getOpcode()) { default: return false; - case Hexagon::STrib_imm_cPt_V4 : - case Hexagon::STrib_imm_cNotPt_V4 : + case Hexagon::S4_storeirbt_io: + case Hexagon::S4_storeirbf_io: case Hexagon::S4_pstorerbt_rr: case Hexagon::S4_pstorerbf_rr: case Hexagon::S2_pstorerbt_io: @@ -1436,16 +1436,16 @@ isConditionalStore (const MachineInstr* MI) const { case Hexagon::S2_pstorerdf_pi: case Hexagon::S2_pstorerht_io: case Hexagon::S2_pstorerhf_io: - case Hexagon::STrih_imm_cPt_V4 : - case Hexagon::STrih_imm_cNotPt_V4 : + case Hexagon::S4_storeirht_io: + case Hexagon::S4_storeirhf_io: case Hexagon::S4_pstorerht_rr: case Hexagon::S4_pstorerhf_rr: case Hexagon::S2_pstorerht_pi: case Hexagon::S2_pstorerhf_pi: case Hexagon::S2_pstorerit_io: case Hexagon::S2_pstorerif_io: - case Hexagon::STriw_imm_cPt_V4 : - case Hexagon::STriw_imm_cNotPt_V4 : + case Hexagon::S4_storeirit_io: + case Hexagon::S4_storeirif_io: case Hexagon::S4_pstorerit_rr: case Hexagon::S4_pstorerif_rr: case Hexagon::S2_pstorerit_pi: diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td index 3ba0bf5..019e276 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -907,74 +907,123 @@ defm : T_ST_LOff_Pats; // TODO: needs to be implemented. //===----------------------------------------------------------------------===// +// Template class +//===----------------------------------------------------------------------===// +let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8, + opExtendable = 2 in +class T_StoreImm MajOp > + : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8), + mnemonic#"($Rs+#$offset)=#$S8", + [], "", V4LDST_tc_st_SLOT01>, + ImmRegRel, PredNewRel { + bits<5> Rs; + bits<8> S8; + bits<8> offset; + bits<6> offsetBits; + + string OffsetOpStr = !cast(OffsetOp); + let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2}, + !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1}, + /* u6_0Imm */ offset{5-0})); + + let IClass = 0b0011; + + let Inst{27-25} = 0b110; + let Inst{22-21} = MajOp; + let Inst{20-16} = Rs; + let Inst{12-7} = offsetBits; + let Inst{13} = S8{7}; + let Inst{6-0} = S8{6-0}; + } + +let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6, + opExtendable = 3 in +class T_StoreImm_pred MajOp, + bit isPredNot, bit isPredNew > + : STInst <(outs ), + (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6), + !if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ", + ") ")#mnemonic#"($Rs+#$offset)=#$S6", + [], "", V4LDST_tc_st_SLOT01>, + ImmRegRel, PredNewRel { + bits<2> Pv; + bits<5> Rs; + bits<6> S6; + bits<8> offset; + bits<6> offsetBits; + + string OffsetOpStr = !cast(OffsetOp); + let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2}, + !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1}, + /* u6_0Imm */ offset{5-0})); + let isPredicatedNew = isPredNew; + let isPredicatedFalse = isPredNot; + + let IClass = 0b0011; + + let Inst{27-25} = 0b100; + let Inst{24} = isPredNew; + let Inst{23} = isPredNot; + let Inst{22-21} = MajOp; + let Inst{20-16} = Rs; + let Inst{13} = S6{5}; + let Inst{12-7} = offsetBits; + let Inst{6-5} = Pv; + let Inst{4-0} = S6{4-0}; + } + + +//===----------------------------------------------------------------------===// // multiclass for store instructions with base + immediate offset // addressing mode and immediate stored value. // mem[bhw](Rx++#s4:3)=#s8 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6 //===----------------------------------------------------------------------===// -multiclass ST_Imm_Pbase { - let isPredicatedNew = isPredNew in - def NAME : STInst2<(outs), - (ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4), - !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($src2+#$src3) = #$src4", - []>, - Requires<[HasV4T]>; -} -multiclass ST_Imm_Pred { - let isPredicatedFalse = PredNot in { - defm _c#NAME : ST_Imm_Pbase; - // Predicate new - defm _cdn#NAME : ST_Imm_Pbase; - } +multiclass ST_Imm_Pred MajOp, + bit PredNot> { + def _io : T_StoreImm_pred ; + // Predicate new + def new_io : T_StoreImm_pred ; } -let isExtendable = 1, isExtentSigned = 1, hasSideEffects = 0 in -multiclass ST_Imm { +multiclass ST_Imm MajOp> { let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in { - let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in - def NAME#_V4 : STInst2<(outs), - (ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3), - mnemonic#"($src1+#$src2) = #$src3", - []>, - Requires<[HasV4T]>; + def _io : T_StoreImm ; - let opExtendable = 3, opExtentBits = 6, isPredicated = 1 in { - defm Pt_V4 : ST_Imm_Pred; - defm NotPt_V4 : ST_Imm_Pred; - } + defm t : ST_Imm_Pred ; + defm f : ST_Imm_Pred ; } } -let addrMode = BaseImmOffset, InputType = "imm", -validSubTargets = HasV4SubT in { +let hasSideEffects = 0, validSubTargets = HasV4SubT, addrMode = BaseImmOffset, + InputType = "imm", isCodeGenOnly = 0 in { let accessSize = ByteAccess in - defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel, PredNewRel; + defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>; let accessSize = HalfWordAccess in - defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel, PredNewRel; + defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>; let accessSize = WordAccess in - defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel, PredNewRel; + defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>; } let Predicates = [HasV4T], AddedComplexity = 10 in { def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)), - (STrib_imm_V4 IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>; + (S4_storeirb_io IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>; def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1, u6_1ImmPred:$src2)), - (STrih_imm_V4 IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>; + (S4_storeirh_io IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>; def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)), - (STriw_imm_V4 IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>; + (S4_storeiri_io IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>; } let AddedComplexity = 6 in def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)), - (STrib_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>, + (S4_storeirb_io IntRegs:$src1, 0, s8ExtPred:$src2)>, Requires<[HasV4T]>; // memb(Rx++#s4:0:circ(Mu))=Rt @@ -990,7 +1039,7 @@ def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)), // memh(Rs+#s11:1)=Rt.H let AddedComplexity = 6 in def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)), - (STrih_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>, + (S4_storeirh_io IntRegs:$src1, 0, s8ExtPred:$src2)>, Requires<[HasV4T]>; // memh(Rs+Ru<<#u2)=Rt.H @@ -1030,7 +1079,7 @@ def STriw_pred_V4 : STInst2<(outs), let AddedComplexity = 6 in def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)), - (STriw_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>, + (S4_storeiri_io IntRegs:$src1, 0, s8ExtPred:$src2)>, Requires<[HasV4T]>; // memw(Rx++#s4:2)=Rt diff --git a/llvm/test/MC/Disassembler/Hexagon/st.txt b/llvm/test/MC/Disassembler/Hexagon/st.txt index 911326c..d6c37be 100644 --- a/llvm/test/MC/Disassembler/Hexagon/st.txt +++ b/llvm/test/MC/Disassembler/Hexagon/st.txt @@ -47,6 +47,8 @@ 0x9f 0xf5 0x11 0x3b # CHECK: memb(r17 + r21<<#3) = r31 +0x9f 0xca 0x11 0x3c +# CHECK: memb(r17+#21)=#31 0x15 0xd5 0x11 0xa1 # CHECK: memb(r17+#21) = r21 0x02 0xf5 0x11 0xa9 @@ -69,6 +71,16 @@ 0x03 0x40 0x45 0x85 0xff 0xf5 0x11 0x37 # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) memb(r17+r21<<#3) = r31 +0xff 0xca 0x11 0x38 +# CHECK: if (p3) memb(r17+#21)=#31 +0xff 0xca 0x91 0x38 +# CHECK: if (!p3) memb(r17+#21)=#31 +0x03 0x40 0x45 0x85 0xff 0xca 0x11 0x39 +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) memb(r17+#21)=#31 +0x03 0x40 0x45 0x85 0xff 0xca 0x91 0x39 +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) memb(r17+#21)=#31 0xab 0xdf 0x11 0x40 # CHECK: if (p3) memb(r17+#21) = r31 0xab 0xdf 0x11 0x44 @@ -94,6 +106,8 @@ # CHECK: memh(r17 + r21<<#3) = r31 0x9f 0xf5 0x71 0x3b # CHECK: memh(r17 + r21<<#3) = r31.h +0x95 0xcf 0x31 0x3c +# CHECK: memh(r17+#62)=#21 0x15 0xdf 0x51 0xa1 # CHECK: memh(r17+#42) = r31 0x15 0xdf 0x71 0xa1 @@ -138,6 +152,16 @@ 0x03 0x40 0x45 0x85 0xff 0xf5 0x71 0x37 # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) memh(r17+r21<<#3) = r31.h +0xf5 0xcf 0x31 0x38 +# CHECK: if (p3) memh(r17+#62)=#21 +0xf5 0xcf 0xb1 0x38 +# CHECK: if (!p3) memh(r17+#62)=#21 +0x03 0x40 0x45 0x85 0xf5 0xcf 0x31 0x39 +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) memh(r17+#62)=#21 +0x03 0x40 0x45 0x85 0xf5 0xcf 0xb1 0x39 +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) memh(r17+#62)=#21 0xfb 0xd5 0x51 0x40 # CHECK: if (p3) memh(r17+#62) = r21 0xfb 0xd5 0x71 0x40 @@ -181,6 +205,8 @@ 0x9f 0xf5 0x91 0x3b # CHECK: memw(r17 + r21<<#3) = r31 +0x9f 0xca 0x51 0x3c +# CHECK: memw(r17+#84)=#31 0x15 0xdf 0x91 0xa1 # CHECK: memw(r17+#84) = r31 0x02 0xf5 0x91 0xa9 @@ -203,6 +229,16 @@ 0x03 0x40 0x45 0x85 0xff 0xf5 0x91 0x37 # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) memw(r17+r21<<#3) = r31 +0xff 0xca 0x51 0x38 +# CHECK: if (p3) memw(r17+#84)=#31 +0xff 0xca 0xd1 0x38 +# CHECK: if (!p3) memw(r17+#84)=#31 +0x03 0x40 0x45 0x85 0xff 0xca 0x51 0x39 +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) memw(r17+#84)=#31 +0x03 0x40 0x45 0x85 0xff 0xca 0xd1 0x39 +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) memw(r17+#84)=#31 0xab 0xdf 0x91 0x40 # CHECK: if (p3) memw(r17+#84) = r31 0xab 0xdf 0x91 0x44 -- 2.7.4