From 2b94a36d5da43bbcc494f7d25f0c379069a85d9b Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Wed, 7 Nov 2018 08:47:21 +0000 Subject: [PATCH] Add support for Loongson 3A1000 processor. gcc/ * config/mips/loongson3a.md: Rename to ... * config/mips/gs464.md: ... here. * config/mips/mips-cpus.def: Define gs464; Add loongson3a as an alias of gs464 processor. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_issue_rate): Use PROCESSOR_GS464 instead of PROCESSOR_LOONGSON_3A. (mips_multipass_dfa_lookahead): Use TUNE_GS464 instead of TUNE_LOONGSON_3A. (mips_option_override): Enable MMI and EXT for gs464. * config/mips/mips.h: Rename TARGET_LOONGSON_3A to TARGET_GS464; Rename TUNE_LOONGSON_3A to TUNE_GS464. (MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464. (ISA_HAS_ODD_SPREG, ISA_AVOID_DIV_HILO, ISA_HAS_FUSED_MADD4, ISA_HAS_UNFUSED_MADD4): Use TARGET_GS464 instead of TARGET_LOONGSON_3A. * config/mips/mips.md: Include gs464.md instead of loongson3a.md. (processor): Add gs464; * doc/invoke.texi: Add gs464 to supported architectures. From-SVN: r265865 --- gcc/ChangeLog | 22 +++++++ gcc/config/mips/gs464.md | 137 ++++++++++++++++++++++++++++++++++++++++ gcc/config/mips/loongson3a.md | 137 ---------------------------------------- gcc/config/mips/mips-cpus.def | 3 +- gcc/config/mips/mips-tables.opt | 19 +++--- gcc/config/mips/mips.c | 6 +- gcc/config/mips/mips.h | 17 ++--- gcc/config/mips/mips.md | 4 +- gcc/doc/invoke.texi | 2 +- 9 files changed, 187 insertions(+), 160 deletions(-) create mode 100644 gcc/config/mips/gs464.md delete mode 100644 gcc/config/mips/loongson3a.md diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6a997fd..4247c67 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,27 @@ 2018-11-07 Chenghua Xu + * config/mips/loongson3a.md: Rename to ... + * config/mips/gs464.md: ... here. + * config/mips/mips-cpus.def: Define gs464; Add loongson3a + as an alias of gs464 processor. + * config/mips/mips-tables.opt: Regenerate. + * config/mips/mips.c (mips_issue_rate): Use PROCESSOR_GS464 + instead of PROCESSOR_LOONGSON_3A. + (mips_multipass_dfa_lookahead): Use TUNE_GS464 instead of + TUNE_LOONGSON_3A. + (mips_option_override): Enable MMI and EXT for gs464. + * config/mips/mips.h: Rename TARGET_LOONGSON_3A to TARGET_GS464; + Rename TUNE_LOONGSON_3A to TUNE_GS464. + (MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464. + (ISA_HAS_ODD_SPREG, ISA_AVOID_DIV_HILO, ISA_HAS_FUSED_MADD4, + ISA_HAS_UNFUSED_MADD4): Use TARGET_GS464 instead of + TARGET_LOONGSON_3A. + * config/mips/mips.md: Include gs464.md instead of loongson3a.md. + (processor): Add gs464; + * doc/invoke.texi: Add gs464 to supported architectures. + +2018-11-07 Chenghua Xu + * config/mips/mips-protos.h (mips_loongson_ext2_prefetch_cookie): New prototype. * config/mips/mips.c (mips_loongson_ext2_prefetch_cookie): New. diff --git a/gcc/config/mips/gs464.md b/gcc/config/mips/gs464.md new file mode 100644 index 0000000..82efb66 --- /dev/null +++ b/gcc/config/mips/gs464.md @@ -0,0 +1,137 @@ +;; Pipeline model for Loongson gs464 cores. + +;; Copyright (C) 2011-2018 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; Uncomment the following line to output automata for debugging. +;; (automata_option "v") + +;; Automaton for integer instructions. +(define_automaton "gs464_a_alu") + +;; Automaton for floating-point instructions. +(define_automaton "gs464_a_falu") + +;; Automaton for memory operations. +(define_automaton "gs464_a_mem") + +;; Describe the resources. + +(define_cpu_unit "gs464_alu1" "gs464_a_alu") +(define_cpu_unit "gs464_alu2" "gs464_a_alu") +(define_cpu_unit "gs464_mem" "gs464_a_mem") +(define_cpu_unit "gs464_falu1" "gs464_a_falu") +(define_cpu_unit "gs464_falu2" "gs464_a_falu") + +;; Describe instruction reservations. + +(define_insn_reservation "gs464_arith" 1 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "arith,clz,const,logical, + move,nop,shift,signext,slt")) + "gs464_alu1 | gs464_alu2") + +(define_insn_reservation "gs464_branch" 1 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "branch,jump,call,condmove,trap")) + "gs464_alu1") + +(define_insn_reservation "gs464_mfhilo" 1 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "mfhi,mflo,mthi,mtlo")) + "gs464_alu2") + +;; Operation imul3nc is fully pipelined. +(define_insn_reservation "gs464_imul3nc" 5 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "imul3nc")) + "gs464_alu2") + +(define_insn_reservation "gs464_imul" 7 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "imul,imadd")) + "gs464_alu2 * 7") + +(define_insn_reservation "gs464_idiv_si" 12 + (and (eq_attr "cpu" "gs464") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "SI"))) + "gs464_alu2 * 12") + +(define_insn_reservation "gs464_idiv_di" 25 + (and (eq_attr "cpu" "gs464") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "DI"))) + "gs464_alu2 * 25") + +(define_insn_reservation "gs464_load" 3 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "load")) + "gs464_mem") + +(define_insn_reservation "gs464_fpload" 4 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "load,mfc,mtc")) + "gs464_mem") + +(define_insn_reservation "gs464_prefetch" 0 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "prefetch,prefetchx")) + "gs464_mem") + +(define_insn_reservation "gs464_store" 0 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "store,fpstore,fpidxstore")) + "gs464_mem") + +;; All the fp operations can be executed in FALU1. Only fp add, +;; sub, mul, madd can be executed in FALU2. Try FALU2 firstly. +(define_insn_reservation "gs464_fadd" 6 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "fadd,fmul,fmadd")) + "gs464_falu2 | gs464_falu1") + +(define_insn_reservation "gs464_fcmp" 2 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "fabs,fcmp,fmove,fneg")) + "gs464_falu1") + +(define_insn_reservation "gs464_fcvt" 4 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "fcvt")) + "gs464_falu1") + +(define_insn_reservation "gs464_fdiv_sf" 12 + (and (eq_attr "cpu" "gs464") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "SF"))) + "gs464_falu1 * 12") + +(define_insn_reservation "gs464_fdiv_df" 19 + (and (eq_attr "cpu" "gs464") + (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + (eq_attr "mode" "DF"))) + "gs464_falu1 * 19") + +;; Force single-dispatch for unknown or multi. +(define_insn_reservation "gs464_unknown" 1 + (and (eq_attr "cpu" "gs464") + (eq_attr "type" "unknown,multi,atomic,syncloop")) + "gs464_alu1 + gs464_alu2 + gs464_falu1 + gs464_falu2 + gs464_mem") + +;; End of DFA-based pipeline description for gs464 diff --git a/gcc/config/mips/loongson3a.md b/gcc/config/mips/loongson3a.md deleted file mode 100644 index 2ebde68..0000000 --- a/gcc/config/mips/loongson3a.md +++ /dev/null @@ -1,137 +0,0 @@ -;; Pipeline model for Loongson-3A cores. - -;; Copyright (C) 2011-2018 Free Software Foundation, Inc. -;; -;; This file is part of GCC. -;; -;; GCC is free software; you can redistribute it and/or modify it -;; under the terms of the GNU General Public License as published -;; by the Free Software Foundation; either version 3, or (at your -;; option) any later version. -;; -;; GCC is distributed in the hope that it will be useful, but WITHOUT -;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -;; License for more details. -;; -;; You should have received a copy of the GNU General Public License -;; along with GCC; see the file COPYING3. If not see -;; . - -;; Uncomment the following line to output automata for debugging. -;; (automata_option "v") - -;; Automaton for integer instructions. -(define_automaton "ls3a_a_alu") - -;; Automaton for floating-point instructions. -(define_automaton "ls3a_a_falu") - -;; Automaton for memory operations. -(define_automaton "ls3a_a_mem") - -;; Describe the resources. - -(define_cpu_unit "ls3a_alu1" "ls3a_a_alu") -(define_cpu_unit "ls3a_alu2" "ls3a_a_alu") -(define_cpu_unit "ls3a_mem" "ls3a_a_mem") -(define_cpu_unit "ls3a_falu1" "ls3a_a_falu") -(define_cpu_unit "ls3a_falu2" "ls3a_a_falu") - -;; Describe instruction reservations. - -(define_insn_reservation "ls3a_arith" 1 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "arith,clz,const,logical, - move,nop,shift,signext,slt")) - "ls3a_alu1 | ls3a_alu2") - -(define_insn_reservation "ls3a_branch" 1 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "branch,jump,call,condmove,trap")) - "ls3a_alu1") - -(define_insn_reservation "ls3a_mfhilo" 1 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "mfhi,mflo,mthi,mtlo")) - "ls3a_alu2") - -;; Operation imul3nc is fully pipelined. -(define_insn_reservation "ls3a_imul3nc" 5 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "imul3nc")) - "ls3a_alu2") - -(define_insn_reservation "ls3a_imul" 7 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "imul,imadd")) - "ls3a_alu2 * 7") - -(define_insn_reservation "ls3a_idiv_si" 12 - (and (eq_attr "cpu" "loongson_3a") - (and (eq_attr "type" "idiv") - (eq_attr "mode" "SI"))) - "ls3a_alu2 * 12") - -(define_insn_reservation "ls3a_idiv_di" 25 - (and (eq_attr "cpu" "loongson_3a") - (and (eq_attr "type" "idiv") - (eq_attr "mode" "DI"))) - "ls3a_alu2 * 25") - -(define_insn_reservation "ls3a_load" 3 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "load")) - "ls3a_mem") - -(define_insn_reservation "ls3a_fpload" 4 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "load,mfc,mtc")) - "ls3a_mem") - -(define_insn_reservation "ls3a_prefetch" 0 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "prefetch,prefetchx")) - "ls3a_mem") - -(define_insn_reservation "ls3a_store" 0 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "store,fpstore,fpidxstore")) - "ls3a_mem") - -;; All the fp operations can be executed in FALU1. Only fp add, -;; sub, mul, madd can be executed in FALU2. Try FALU2 firstly. -(define_insn_reservation "ls3a_fadd" 6 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "fadd,fmul,fmadd")) - "ls3a_falu2 | ls3a_falu1") - -(define_insn_reservation "ls3a_fcmp" 2 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "fabs,fcmp,fmove,fneg")) - "ls3a_falu1") - -(define_insn_reservation "ls3a_fcvt" 4 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "fcvt")) - "ls3a_falu1") - -(define_insn_reservation "ls3a_fdiv_sf" 12 - (and (eq_attr "cpu" "loongson_3a") - (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") - (eq_attr "mode" "SF"))) - "ls3a_falu1 * 12") - -(define_insn_reservation "ls3a_fdiv_df" 19 - (and (eq_attr "cpu" "loongson_3a") - (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") - (eq_attr "mode" "DF"))) - "ls3a_falu1 * 19") - -;; Force single-dispatch for unknown or multi. -(define_insn_reservation "ls3a_unknown" 1 - (and (eq_attr "cpu" "loongson_3a") - (eq_attr "type" "unknown,multi,atomic,syncloop")) - "ls3a_alu1 + ls3a_alu2 + ls3a_falu1 + ls3a_falu2 + ls3a_mem") - -;; End of DFA-based pipeline description for loongson_3a diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index 6a54563..eabe045 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -162,7 +162,8 @@ MIPS_CPU ("sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY_SPEED) /* MIPS64 Release 2 processors. */ -MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 65, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("loongson3a", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("gs464", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY_SPEED) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 11be463..3114fce 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -679,26 +679,29 @@ EnumValue Enum(mips_arch_opt_value) String(loongson3a) Value(96) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon) Value(97) Canonical +Enum(mips_arch_opt_value) String(gs464) Value(97) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon+) Value(98) Canonical +Enum(mips_arch_opt_value) String(octeon) Value(98) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon2) Value(99) Canonical +Enum(mips_arch_opt_value) String(octeon+) Value(99) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon3) Value(100) Canonical +Enum(mips_arch_opt_value) String(octeon2) Value(100) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(101) Canonical +Enum(mips_arch_opt_value) String(octeon3) Value(101) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6400) Value(102) Canonical +Enum(mips_arch_opt_value) String(xlp) Value(102) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6500) Value(103) Canonical +Enum(mips_arch_opt_value) String(i6400) Value(103) Canonical EnumValue -Enum(mips_arch_opt_value) String(p6600) Value(104) Canonical +Enum(mips_arch_opt_value) String(i6500) Value(104) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(p6600) Value(105) Canonical diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 1c20750..e6dd379 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -836,7 +836,7 @@ static const struct mips_rtx_cost_data { /* Loongson-2F */ DEFAULT_COSTS }, - { /* Loongson-3A */ + { /* Loongson gs464. */ DEFAULT_COSTS }, { /* M4k */ @@ -14614,7 +14614,7 @@ mips_issue_rate (void) case PROCESSOR_LOONGSON_2E: case PROCESSOR_LOONGSON_2F: - case PROCESSOR_LOONGSON_3A: + case PROCESSOR_GS464: case PROCESSOR_P5600: case PROCESSOR_P6600: return 4; @@ -14746,7 +14746,7 @@ mips_multipass_dfa_lookahead (void) if (TUNE_SB1) return 4; - if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A) + if (TUNE_LOONGSON_2EF || TUNE_GS464) return 4; if (TUNE_OCTEON) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index beeb4bc..9666107 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -266,7 +266,7 @@ struct mips_cpu_info { #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E) #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) -#define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A) +#define TARGET_GS464 (mips_arch == PROCESSOR_GS464) #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) @@ -298,7 +298,7 @@ struct mips_cpu_info { || mips_tune == PROCESSOR_74KF3_2) #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ || mips_tune == PROCESSOR_LOONGSON_2F) -#define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A) +#define TUNE_GS464 (mips_tune == PROCESSOR_GS464) #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) @@ -792,7 +792,8 @@ struct mips_cpu_info { %{march=mips32r6: -mips32r6} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |march=xlr: -mips64} \ - %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \ + %{march=mips64r2|march=loongson3a|march=gs464|march=octeon \ + |march=xlp: -mips64r2} \ %{march=mips64r3: -mips64r3} \ %{march=mips64r5: -mips64r5} \ %{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}" @@ -909,7 +910,7 @@ struct mips_cpu_info { #define MIPS_ASE_LOONGSON_EXT_SPEC \ "%{!mno-loongson-ext: \ - %{march=loongson3a: -mloongson-ext}}" + %{march=loongson3a|march=gs464: -mloongson-ext}}" #define DRIVER_SELF_SPECS \ MIPS_ISA_LEVEL_SPEC, \ @@ -962,7 +963,7 @@ struct mips_cpu_info { /* ISA has 32 single-precision registers. */ #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \ - && !TARGET_LOONGSON_3A) \ + && !TARGET_GS464) \ || TARGET_FLOAT64 \ || TARGET_MIPS5900) @@ -1005,7 +1006,7 @@ struct mips_cpu_info { because the former are faster and can also have the effect of reducing code size. */ #define ISA_AVOID_DIV_HILO ((TARGET_LOONGSON_2EF \ - || TARGET_LOONGSON_3A) \ + || TARGET_GS464) \ && !TARGET_MIPS16) /* ISA supports instructions DDIV and DDIVU. */ @@ -1098,14 +1099,14 @@ struct mips_cpu_info { 'd = [+-] (a * b [+-] c)'. */ #define ISA_HAS_FUSED_MADD4 (mips_madd4 \ && (TARGET_MIPS8000 \ - || TARGET_LOONGSON_3A)) + || TARGET_GS464)) /* ISA has 4 operand unfused madd instructions of the form 'd = [+-] (a * b [+-] c)'. */ #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \ && ISA_HAS_FP4 \ && !TARGET_MIPS8000 \ - && !TARGET_LOONGSON_3A) + && !TARGET_GS464) /* ISA has 3 operand r6 fused madd instructions of the form 'c = c [+-] (a * b)'. */ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 8358218..d347a25 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -37,7 +37,7 @@ 74kf3_2 loongson_2e loongson_2f - loongson_3a + gs464 m4k octeon octeon2 @@ -1173,7 +1173,7 @@ (include "9000.md") (include "10000.md") (include "loongson2ef.md") -(include "loongson3a.md") +(include "gs464.md") (include "octeon.md") (include "sb1.md") (include "sr71k.md") diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 7e5bc7e..b300169 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -20798,7 +20798,7 @@ The processor names are: @samp{1004kc}, @samp{1004kf2_1}, @samp{1004kf1_1}, @samp{i6400}, @samp{i6500}, @samp{interaptiv}, -@samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, +@samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, @samp{gs464}, @samp{m4k}, @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, @samp{m5100}, @samp{m5101}, -- 2.7.4