From 2b7e167bbdfa8bcdb826309698acee3f96c02331 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Sat, 28 May 2022 18:09:56 +0800 Subject: [PATCH] radeonsi: enable PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This can remove special handling of tessfactors which also benifit the nir lower pass which does not handle these as system value. Reviewed-by: Marek Olšák Acked-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Timur Kristóf Signed-off-by: Qiang Yu Part-of: --- src/amd/llvm/ac_nir_to_llvm.c | 2 -- src/gallium/drivers/radeonsi/si_get.c | 1 + src/gallium/drivers/radeonsi/si_shader_info.c | 15 +++++---------- src/gallium/drivers/radeonsi/si_shader_llvm.c | 7 ------- 4 files changed, 6 insertions(+), 19 deletions(-) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 00511ab..f5c473e 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -3611,8 +3611,6 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins case nir_intrinsic_load_base_vertex: case nir_intrinsic_load_first_vertex: case nir_intrinsic_load_workgroup_size: - case nir_intrinsic_load_tess_level_outer: - case nir_intrinsic_load_tess_level_inner: case nir_intrinsic_load_tess_level_outer_default: case nir_intrinsic_load_tess_level_inner_default: case nir_intrinsic_load_tess_rel_patch_id_amd: diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index 44a3be0..fcd4fd7 100644 --- a/src/gallium/drivers/radeonsi/si_get.c +++ b/src/gallium/drivers/radeonsi/si_get.c @@ -165,6 +165,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_IMAGE_STORE_FORMATTED: case PIPE_CAP_ALLOW_DRAW_OUT_OF_ORDER: case PIPE_CAP_QUERY_SO_OVERFLOW: + case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS: return 1; case PIPE_CAP_TEXTURE_TRANSFER_MODES: diff --git a/src/gallium/drivers/radeonsi/si_shader_info.c b/src/gallium/drivers/radeonsi/si_shader_info.c index ff4b74e..f4d94f0 100644 --- a/src/gallium/drivers/radeonsi/si_shader_info.c +++ b/src/gallium/drivers/radeonsi/si_shader_info.c @@ -440,8 +440,6 @@ static void scan_instruction(const struct nir_shader *nir, struct si_shader_info break; case nir_intrinsic_load_barycentric_at_sample: /* This loads sample positions. */ - case nir_intrinsic_load_tess_level_outer: /* TES input read from memory */ - case nir_intrinsic_load_tess_level_inner: /* TES input read from memory */ info->uses_vmem_load_other = true; break; @@ -625,6 +623,11 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir, info->tessfactors_are_def_in_all_invocs = are_tessfactors_def_in_all_invocs(nir); } + /* tess factors are loaded as input instead of system value */ + info->reads_tess_factors = nir->info.patch_inputs_read & + (BITFIELD64_BIT(VARYING_SLOT_TESS_LEVEL_INNER) | + BITFIELD64_BIT(VARYING_SLOT_TESS_LEVEL_OUTER)); + info->uses_frontface = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRONT_FACE); info->uses_instanceid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID); info->uses_base_vertex = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_VERTEX); @@ -639,8 +642,6 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir, info->uses_primid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID) || nir->info.inputs_read & VARYING_BIT_PRIMITIVE_ID; info->reads_samplemask = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN); - info->reads_tess_factors = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_TESS_LEVEL_INNER) || - BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_TESS_LEVEL_OUTER); info->uses_linear_sample = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE); info->uses_linear_centroid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID); info->uses_linear_center = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL); @@ -686,12 +687,6 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir, info->output_usagemask[info->num_outputs] = 0x1; } - if (nir->info.stage == MESA_SHADER_TESS_EVAL) { - /* This is a hack to simplify loading tess levels in TES. */ - info->input[info->num_inputs].semantic = VARYING_SLOT_TESS_LEVEL_OUTER; - info->input[info->num_inputs + 1].semantic = VARYING_SLOT_TESS_LEVEL_INNER; - } - if (nir->info.stage == MESA_SHADER_FRAGMENT) { info->allow_flat_shading = !(info->uses_persp_center || info->uses_persp_centroid || info->uses_persp_sample || info->uses_linear_center || diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm.c b/src/gallium/drivers/radeonsi/si_shader_llvm.c index a1de3d8..b52cfad 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm.c @@ -718,7 +718,6 @@ void si_build_wrapper_function(struct si_shader_context *ctx, LLVMValueRef *part static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrinsic_op op) { struct si_shader_context *ctx = si_shader_context_from_abi(abi); - const struct si_shader_info *info = &ctx->shader->selector->info; switch (op) { case nir_intrinsic_load_first_vertex: @@ -746,12 +745,6 @@ static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrin return ac_build_gather_values(&ctx->ac, chan, 3); } - case nir_intrinsic_load_tess_level_outer: - return abi->load_tess_varyings(abi, ctx->ac.f32, NULL, NULL, info->num_inputs, 0, 4, true); - - case nir_intrinsic_load_tess_level_inner: - return abi->load_tess_varyings(abi, ctx->ac.f32, NULL, NULL, info->num_inputs + 1, 0, 4, true); - case nir_intrinsic_load_tess_level_outer_default: case nir_intrinsic_load_tess_level_inner_default: { LLVMValueRef slot = LLVMConstInt(ctx->ac.i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0); -- 2.7.4