From 2b427c722a66bd4766e19a897c1ce81b184d41e8 Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Thu, 28 Dec 2017 14:30:33 +0900 Subject: [PATCH] arm: sc8830: remove build warnings Remove build warnings from sc8830 arch bsp code. Change-Id: I253660a28de843f9f0e61ce7d5bd0a75cf05a86b Signed-off-by: Seung-Woo Kim --- arch/arm/cpu/armv7/sc8830/Tshark_boot_cp.c | 4 +- arch/arm/cpu/armv7/sc8830/adi.c | 2 +- arch/arm/cpu/armv7/sc8830/ana_efuse.c | 4 -- arch/arm/cpu/armv7/sc8830/check_reboot.c | 46 +++++++++++-------- .../armv7/sc8830/chip_x30g/chip_phy_x30g.c | 17 +++---- arch/arm/cpu/armv7/sc8830/clock.c | 33 +++++-------- arch/arm/cpu/armv7/sc8830/dcdc_cal_sc2723.c | 6 +-- arch/arm/cpu/armv7/sc8830/eic.c | 14 ++---- arch/arm/cpu/armv7/sc8830/glb.c | 1 - arch/arm/cpu/armv7/sc8830/gpio.c | 11 ----- arch/arm/cpu/armv7/sc8830/misc.c | 45 ++++++++++-------- arch/arm/cpu/armv7/sc8830/otp-helper.c | 3 ++ arch/arm/cpu/armv7/sc8830/watchdog.c | 8 ++++ arch/arm/cpu/armv7/sc8830/watchdog_hal.c | 21 ++++----- arch/arm/cpu/armv7/sc8830/watchdog_phy_v3.c | 6 +-- .../arm/include/asm/arch-sc8830/boot_drvapi.h | 2 +- arch/arm/include/asm/arch-sc8830/gpio_phy.h | 7 +++ 17 files changed, 111 insertions(+), 119 deletions(-) diff --git a/arch/arm/cpu/armv7/sc8830/Tshark_boot_cp.c b/arch/arm/cpu/armv7/sc8830/Tshark_boot_cp.c index db67971..d823155 100644 --- a/arch/arm/cpu/armv7/sc8830/Tshark_boot_cp.c +++ b/arch/arm/cpu/armv7/sc8830/Tshark_boot_cp.c @@ -6,7 +6,7 @@ static u32 state; void boot_cp0(void) { u32 m_data[3] = {0xe59f0000, 0xe12fff10, MODEM_ADR}; - memcpy(CP0_CODE_COPY_ADR, m_data, sizeof(m_data)); /* copy cp0 source code */ + memcpy((u32 *)CP0_CODE_COPY_ADR, m_data, sizeof(m_data)); /* copy cp0 source code */ *((volatile u32*)COOPERATE_PMU_CTRL0_ADDR) &= ~BIT_25; /* open cp0 pmu controller*/ msleep(50); @@ -32,7 +32,7 @@ void boot_cp1(void); void boot_cp2(void) { u32 wcndata[3] = {0xe59f0000, 0xe12fff10, WCNMODEM_ADR}; - memcpy(CP2_CODE_COPY_ADR, wcndata, sizeof(wcndata)); /* copy cp2 source code */ + memcpy((u32 *)CP2_CODE_COPY_ADR, wcndata, sizeof(wcndata)); /* copy cp2 source code */ *((volatile u32*)COOPERATE_PMU_CTRL2_ADDR) &= ~BIT_25; /* open cp2 pmu controller*/ msleep(50); diff --git a/arch/arm/cpu/armv7/sc8830/adi.c b/arch/arm/cpu/armv7/sc8830/adi.c index d86400f..f4cacda 100644 --- a/arch/arm/cpu/armv7/sc8830/adi.c +++ b/arch/arm/cpu/armv7/sc8830/adi.c @@ -169,7 +169,7 @@ static inline int __adi_read(u32 regPddr) if (cnt + 1 <= 0){ while(1){ - printf("[0x%s]: ADI READ timeout!!! reg = 0x%x, value = 0x%x\n", __func__, regPddr, val); + printf("[0x%s]: ADI READ timeout!!! reg = 0x%x, value = 0x%lx\n", __func__, regPddr, val); udelay(1000000); } } diff --git a/arch/arm/cpu/armv7/sc8830/ana_efuse.c b/arch/arm/cpu/armv7/sc8830/ana_efuse.c index 8fff484..080c4ef 100644 --- a/arch/arm/cpu/armv7/sc8830/ana_efuse.c +++ b/arch/arm/cpu/armv7/sc8830/ana_efuse.c @@ -82,10 +82,6 @@ static void adie_efuse_unlock(void) { } -static void adie_efuse_reset(void) -{ -} - static void __adie_efuse_power_on(void) { sci_adi_set(ANA_REG_GLB_ARM_MODULE_EN, BIT_ANA_EFS_EN); diff --git a/arch/arm/cpu/armv7/sc8830/check_reboot.c b/arch/arm/cpu/armv7/sc8830/check_reboot.c index f751d8f..7a936e4 100644 --- a/arch/arm/cpu/armv7/sc8830/check_reboot.c +++ b/arch/arm/cpu/armv7/sc8830/check_reboot.c @@ -1,3 +1,4 @@ +#include #include #include #include @@ -36,15 +37,20 @@ #define debugf(fmt, args...) #endif - extern int hw_watchdog_rst_pending(void); -extern inline int is_7s_reset(void); +extern int is_7s_reset(void); extern int is_7s_reset_for_systemdump(void); -extern inline int is_hw_smpl_enable(void); +extern int is_hw_smpl_enable(void); __attribute__ ((gnu_inline))inline int is_smpl_bootup(void); +extern void reset_cpu(ulong ignored); +extern void power_down_cpu(ulong ignored); +extern int sci_glb_set(u32 reg, u32 bit); +extern int sprd_eic_get(unsigned offset); +extern int sprd_eic_request(unsigned offset); + unsigned check_reboot_mode(void) { - unsigned val, rst_mode= 0; + unsigned rst_mode= 0; unsigned hw_rst_mode = ANA_REG_GET(ANA_REG_GLB_POR_SRC_FLAG); debugf("hw_rst_mode==%x\n", hw_rst_mode); @@ -120,7 +126,22 @@ unsigned check_reboot_mode(void) } -int get_mode_from_gpio() +int charger_connected(void) +{ + sprd_eic_request(EIC_CHG_INT); + udelay(3000); + debugf("eica status %x\n", sprd_eic_get(EIC_CHG_INT)); +#ifdef CONFIG_SHARK_PAD_HW_V102 + sprd_eic_request(EIC_USB_DETECT); + udelay(3000); + debugf("eica status %x\n", sprd_eic_get(EIC_USB_DETECT)); + return (!!sprd_eic_get(EIC_USB_DETECT)) ||(!!sprd_eic_get(EIC_CHG_INT)); +#else + return !!sprd_eic_get(EIC_CHG_INT); +#endif +} + +int get_mode_from_gpio(void) { int ret = 0; unsigned hw_rst_mode; @@ -187,21 +208,6 @@ int power_button_pressed(void) } -int charger_connected(void) -{ - sprd_eic_request(EIC_CHG_INT); - udelay(3000); - debugf("eica status %x\n", sprd_eic_get(EIC_CHG_INT)); -#ifdef CONFIG_SHARK_PAD_HW_V102 - sprd_eic_request(EIC_USB_DETECT); - udelay(3000); - debugf("eica status %x\n", sprd_eic_get(EIC_USB_DETECT)); - return (!!sprd_eic_get(EIC_USB_DETECT)) ||(!!sprd_eic_get(EIC_CHG_INT)); -#else - return !!sprd_eic_get(EIC_CHG_INT); -#endif -} - int alarm_triggered(void) { //printf("ANA_RTC_INT_RSTS is 0x%x\n", ANA_RTC_INT_RSTS); diff --git a/arch/arm/cpu/armv7/sc8830/chip_x30g/chip_phy_x30g.c b/arch/arm/cpu/armv7/sc8830/chip_x30g/chip_phy_x30g.c index 57c5639..de834a1 100644 --- a/arch/arm/cpu/armv7/sc8830/chip_x30g/chip_phy_x30g.c +++ b/arch/arm/cpu/armv7/sc8830/chip_x30g/chip_phy_x30g.c @@ -18,6 +18,7 @@ /**---------------------------------------------------------------------------* ** Dependencies * **---------------------------------------------------------------------------*/ +#include #include #include "asm/arch/sc_reg.h" #include "asm/arch/adi_hal_internal.h" @@ -56,6 +57,8 @@ struct dcdc_core_ds_step_info{ /**---------------------------------------------------------------------------* ** Function Definitions * **---------------------------------------------------------------------------*/ +extern int calibrate_register_callback(void *callback_fun); + /*****************************************************************************/ // Description : This function is used to reset MCU. // Global resource dependence : @@ -200,7 +203,7 @@ PUBLIC void CHIP_PHY_SetWDGHWFlag (WDG_HW_FLAG_T type, uint32 val) // Author: Jeff.Li // Note: Do nothing. There are 32KB internal ram dedicated for ARM. /*****************************************************************************/ -PUBLIC void CHIP_PHY_BootIramEn () +PUBLIC void CHIP_PHY_BootIramEn (void) { } @@ -233,7 +236,7 @@ PUBLIC BOOLEAN CHIP_PHY_IsWDGRstByMCU (uint32 flag) // Note : | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 | // |ALL_HRST_MONITOR | POR_HRST_MONITOR| WDG_HRST_MONITOR | /*****************************************************************************/ -PUBLIC BOOLEAN CHIP_PHY_IsResetByPowerUp() +PUBLIC BOOLEAN CHIP_PHY_IsResetByPowerUp(void) { if ((CHIP_PHY_GetANAReg () & 0xF0) == 0x0) { @@ -252,7 +255,7 @@ PUBLIC BOOLEAN CHIP_PHY_IsResetByPowerUp() // Note : | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 | // |ALL_HRST_MONITOR | POR_HRST_MONITOR| WDG_HRST_MONITOR | /*****************************************************************************/ -PUBLIC BOOLEAN CHIP_PHY_IsResetByWatchDog() +PUBLIC BOOLEAN CHIP_PHY_IsResetByWatchDog(void) { if ((CHIP_PHY_GetANAReg () & 0xF) == 0x0) { @@ -717,9 +720,9 @@ static void dcdc_optimize_config(unsigned int para) static void dcdc_core_ds_config(unsigned int para) { #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723) +#if 0 uint32 dcdc_core_ctl_adi = 0; uint32 reg_val = 0; -#if 0 uint32 dcdc_core_ctl_ds = -1; uint32 dcdc_core_cal_adi = 0; uint32 reg_val_cal = 0; @@ -843,9 +846,9 @@ struct ddr_phy_lp_reg_ctrl lp_cfg= 0x00000007, #endif 0x99998888, - 0x402b006c, + {0x402b006c, 0x402b0140, - 0x402b0144 + 0x402b0144} }; static unsigned int dmc_phy_is_auto_pd(unsigned int is_auto_pd) { @@ -865,8 +868,6 @@ static unsigned int dmc_phy_is_auto_pd(unsigned int is_auto_pd) static void setup_ap_cp_sync_sleep_code(unsigned int start_addr) { #ifndef CONFIG_SPX20 - unsigned int *sa = (unsigned int*)start_addr; - dmc_phy_is_auto_pd(lp_cfg.is_auto_pd); #endif /*enable cp2 can access 0x50001800*/ diff --git a/arch/arm/cpu/armv7/sc8830/clock.c b/arch/arm/cpu/armv7/sc8830/clock.c index 2496a67..6a25432 100644 --- a/arch/arm/cpu/armv7/sc8830/clock.c +++ b/arch/arm/cpu/armv7/sc8830/clock.c @@ -17,10 +17,6 @@ #define __ffs(x) (ffs(x) - 1) -#define DEFINE_SPINLOCK(...) -#define spin_lock_irqsave(...) -#define spin_unlock_irqrestore(...) - #include #include #include @@ -36,7 +32,11 @@ const u32 __clkinit2 __clkinit_end = &CLK_LK_clk_mpll; //#define debug0 printf -DEFINE_SPINLOCK(clocks_lock); +extern void clkdev_add(struct clk_lookup *cl); +extern int sci_glb_set(u32 reg, u32 bit); +extern int sci_glb_clr(u32 reg, u32 bit); +extern u32 sci_glb_read(u32 reg, u32 msk); +extern int sci_glb_write(u32 reg, u32 val, u32 msk); int clk_enable(struct clk *clk) { @@ -46,10 +46,8 @@ int clk_enable(struct clk *clk) clk_enable(clk->parent); - spin_lock_irqsave(&clocks_lock, flags); if ((clk->usage++) == 0 && clk->enable) (clk->enable) (clk, 1, &flags); - spin_unlock_irqrestore(&clocks_lock, flags); debug0("clk %p, usage %d\n", clk, clk->usage); return 0; } @@ -62,16 +60,13 @@ void clk_disable(struct clk *clk) if (IS_ERR_OR_NULL(clk)) return; - spin_lock_irqsave(&clocks_lock, flags); if ((--clk->usage) == 0 && clk->enable) (clk->enable) (clk, 0, &flags); if (WARN(clk->usage < 0, "warning: clock (%s) usage (%d)\n", clk->regs->name, clk->usage)) { clk->usage = 0; /* force reset clock refcnt */ - spin_unlock_irqrestore(&clocks_lock, flags); return; } - spin_unlock_irqrestore(&clocks_lock, flags); debug0("clk %p, usage %d\n", clk, clk->usage); clk_disable(clk->parent); } @@ -135,7 +130,6 @@ EXPORT_SYMBOL(clk_round_rate); int clk_set_rate(struct clk *clk, unsigned long rate) { int ret; - unsigned long flags; debug0("clk %p, rate %lu\n", clk, rate); if (IS_ERR_OR_NULL(clk) || rate == 0) return -EINVAL; @@ -150,9 +144,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate) if (clk->ops == NULL || clk->ops->set_rate == NULL) return -EINVAL; - spin_lock_irqsave(&clocks_lock, flags); ret = (clk->ops->set_rate) (clk, rate); - spin_unlock_irqrestore(&clocks_lock, flags); return ret; } @@ -168,7 +160,6 @@ EXPORT_SYMBOL(clk_get_parent); int clk_set_parent(struct clk *clk, struct clk *parent) { int ret = -EACCES; - unsigned long flags; #if defined(CONFIG_DEBUG_FS) struct clk *old_parent = clk_get_parent(clk); debug0("clk %p, parent %p <<< %p\n", clk, parent, old_parent); @@ -176,10 +167,8 @@ int clk_set_parent(struct clk *clk, struct clk *parent) if (IS_ERR_OR_NULL(clk) || IS_ERR(parent)) return -EINVAL; - spin_lock_irqsave(&clocks_lock, flags); if (clk->ops && clk->ops->set_parent) ret = (clk->ops->set_parent) (clk, parent); - spin_unlock_irqrestore(&clocks_lock, flags); #if defined(CONFIG_DEBUG_FS) /* FIXME: call debugfs_rename() out of spin lock, @@ -209,14 +198,10 @@ static int sci_clk_enable(struct clk *c, int enable, unsigned long *pflags) enable = !enable; if (!c->regs->enb.mask) { /* enable matrix clock */ - if (pflags) - spin_unlock_irqrestore(&clocks_lock, *pflags); if (enable) clk_enable((struct clk *)c->regs->enb.reg); else clk_disable((struct clk *)c->regs->enb.reg); - if (pflags) - spin_lock_irqsave(&clocks_lock, *pflags); } else { if (enable) sci_glb_set(c->regs->enb.reg & ~1, c->regs->enb.mask); @@ -449,6 +434,7 @@ int __init sci_clk_register(struct clk_lookup *cl) return 0; } +#ifdef CONFIG_NKERNEL static int __init sci_clock_dump(void) { struct clk_lookup *cl = (struct clk_lookup *)(&__clkinit_begin + 1); @@ -464,8 +450,10 @@ static int __init sci_clock_dump(void) } return 0; } +#endif -static int __clk_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data) +#if 0 +static int __clk_cpufreq_notifier(struct notifier_block nb, unsigned long val, void *data) { struct cpufreq_freqs *freq = data; @@ -479,6 +467,7 @@ static int __clk_cpufreq_notifier(struct notifier_block *nb, unsigned long val, static struct notifier_block __clk_cpufreq_notifier_block = { .notifier_call = __clk_cpufreq_notifier }; +#endif int __init sci_clock_init(void) { @@ -514,7 +503,7 @@ int __init sci_clock_init(void) return 0; } -#ifndef CONFIG_NKERNEL +#ifdef CONFIG_NKERNEL arch_initcall(sci_clock_init); late_initcall_sync(sci_clock_dump); #endif diff --git a/arch/arm/cpu/armv7/sc8830/dcdc_cal_sc2723.c b/arch/arm/cpu/armv7/sc8830/dcdc_cal_sc2723.c index 2c2babe..01aa8d6 100644 --- a/arch/arm/cpu/armv7/sc8830/dcdc_cal_sc2723.c +++ b/arch/arm/cpu/armv7/sc8830/dcdc_cal_sc2723.c @@ -782,11 +782,11 @@ typedef struct { }vol_para_t; #if defined(CONFIG_FDL2_BUILD) -vol_para_t **ppvol_para = 0x50000020; +vol_para_t **ppvol_para = (vol_para_t **)0x50000020; #elif defined(CONFIG_SPL_32K) -vol_para_t **ppvol_para = 0x50003C20; +vol_para_t **ppvol_para = (vol_para_t **)0x50003C20; #else -vol_para_t **ppvol_para = 0x50003C20; +vol_para_t **ppvol_para = (vol_para_t **)0x50003C20; #endif static int get_vol_para_num(void) diff --git a/arch/arm/cpu/armv7/sc8830/eic.c b/arch/arm/cpu/armv7/sc8830/eic.c index 7b8a94a..65f5949 100644 --- a/arch/arm/cpu/armv7/sc8830/eic.c +++ b/arch/arm/cpu/armv7/sc8830/eic.c @@ -11,6 +11,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include #include #include #include @@ -22,9 +23,7 @@ #define KERN_WARNING "" #define WARN(nmu, fmt...) printf(fmt) #define WARN_ON(num) -#define BUG_ON(__cond__) if(__cond__) printf("%s line: %d bug on\n", __FUNCTION__, __LINE__) #define pr_err(fmt...) printf(fmt) -#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0])) #define pr_debug(fmt...) printf(fmt) //#define DEBUG @@ -76,10 +75,6 @@ enum eic_die { static void __get_eic_base_info (u32 eic_id, struct eic_info *info) { - int i = 0; - u32 table_size = 0; - struct gpio_section *section_table; - if (eic_id>=SPRD_ADIE_EIC_START && eic_id<=SPRD_ADIE_EIC_END) { info->base_addr= SPRD_ANA_EIC_PHYS; @@ -105,7 +100,6 @@ static void __get_eic_base_info (u32 eic_id, struct eic_info *info) static int __eic_get_pin_data (struct eic_info *info) { - u32 offset_addr = 0; u32 reg_addr = 0, reg_data; if (info->base_addr == INVALID_REG) @@ -126,7 +120,6 @@ static int __eic_get_pin_data (struct eic_info *info) static int __eic_get_data_mask (struct eic_info *info) { - u32 offset_addr = 0; u32 reg_addr = 0, reg_data; if (info->base_addr == INVALID_REG) @@ -150,7 +143,6 @@ static int __eic_get_data_mask (struct eic_info *info) */ static void __eic_set_data_mask (struct eic_info *info, int b_on) { - u32 offset_addr = 0; u32 reg_addr = 0, reg_data; reg_addr = info->base_addr + EIC_MASK; @@ -223,6 +215,7 @@ int sprd_eic_request(unsigned offset) return 0; } +#if 0 static void sprd_eic_free(unsigned offset) { unsigned eic_id = offset; @@ -232,6 +225,7 @@ static void sprd_eic_free(unsigned offset) __eic_set_data_mask (&gpio_info, 0); return; } +#endif void sprd_eic_init(void) { @@ -241,7 +235,7 @@ void sprd_eic_init(void) ANA_REG_OR(ANA_REG_GLB_RTC_CLK_EN, BIT_RTC_EIC_EN); } -int get_volumn_down_status2() +int get_volumn_down_status2(void) { int temp_cnt = 600; int status = 0; diff --git a/arch/arm/cpu/armv7/sc8830/glb.c b/arch/arm/cpu/armv7/sc8830/glb.c index 6e666a2..c5ee2a2 100644 --- a/arch/arm/cpu/armv7/sc8830/glb.c +++ b/arch/arm/cpu/armv7/sc8830/glb.c @@ -37,7 +37,6 @@ u32 sci_glb_read(u32 reg, u32 msk) int sci_glb_write(u32 reg, u32 val, u32 msk) { - unsigned long flags, hw_flags; __raw_writel((__raw_readl(reg) & ~msk) | val, reg); return 0; } diff --git a/arch/arm/cpu/armv7/sc8830/gpio.c b/arch/arm/cpu/armv7/sc8830/gpio.c index 3ea3b1e..dd6b536 100644 --- a/arch/arm/cpu/armv7/sc8830/gpio.c +++ b/arch/arm/cpu/armv7/sc8830/gpio.c @@ -80,7 +80,6 @@ static void __gpio_set_dir (struct gpio_info * info, int dir) { int value = !!dir; u32 reg_addr = 0; - unsigned long flags; reg_addr = info->base_addr; @@ -106,7 +105,6 @@ static void __gpio_set_dir (struct gpio_info * info, int dir) return; } - //local_irq_save(flags); value = gpio_reg_get(reg_addr, info->die); if (dir) @@ -114,8 +112,6 @@ static void __gpio_set_dir (struct gpio_info * info, int dir) else value &= ~(1 << info->bit_num); gpio_reg_set(reg_addr, info->die, value); - - //local_irq_restore(flags); } /* @@ -244,7 +240,6 @@ static void __gpio_set_pin_data (struct gpio_info *info ,int b_on) u32 offset_addr; u32 reg_addr; int value; - unsigned long flags; reg_addr = info->base_addr; @@ -254,15 +249,12 @@ static void __gpio_set_pin_data (struct gpio_info *info ,int b_on) reg_addr += offset_addr; - //local_irq_save(flags); - value = gpio_reg_get(reg_addr, info->die); if (b_on) value |= 1 << info->bit_num; else value &= ~(1 << info->bit_num); gpio_reg_set(reg_addr, info->die, value); - //local_irq_restore(flags); } /* @@ -273,21 +265,18 @@ static void __gpio_set_data_mask (struct gpio_info *info, int b_on) int value; u32 reg_addr; u32 offset_addr; - unsigned long flags; reg_addr = info->base_addr; offset_addr = __gpio_get_data_mask_reg_offs(info); if (offset_addr != INVALID_REG) { reg_addr += offset_addr; - //local_irq_save(flags); value = gpio_reg_get(reg_addr, info->die); if (b_on) value |= 1 << info->bit_num; else value &= ~(1 << info->bit_num); gpio_reg_set(reg_addr, info->die, value); - //local_irq_restore(flags); GPIO_DBG("After setting gpio_addr %x data mask :%x\r\n", reg_addr, gpio_reg_get(reg_addr, info->die)); diff --git a/arch/arm/cpu/armv7/sc8830/misc.c b/arch/arm/cpu/armv7/sc8830/misc.c index fbe348f..e3559e4 100644 --- a/arch/arm/cpu/armv7/sc8830/misc.c +++ b/arch/arm/cpu/armv7/sc8830/misc.c @@ -3,6 +3,9 @@ #include #include #include + +extern void __raw_bits_or(unsigned int v, unsigned int a); + /* REG_AON_APB_BOND_OPT0 ==> romcode set REG_AON_APB_BOND_OPT1 ==> set it later @@ -20,7 +23,7 @@ * 1 : enable jtag success * * 0 : enable jtag fail * *************************************************/ -int sprd_jtag_enable() +int sprd_jtag_enable(void) { if (*((volatile unsigned int *)(REG_AON_APB_BOND_OPT0)) & 1) { @@ -35,7 +38,7 @@ int sprd_jtag_enable() * 1 : disable jtag success * * 0 : disable jtag fail * *************************************************/ -int sprd_jtag_disable() +int sprd_jtag_disable(void) { if (!(*((volatile unsigned int *)(REG_AON_APB_BOND_OPT0)) & 1)) { @@ -51,42 +54,44 @@ int sprd_jtag_disable() } } -static void ap_slp_cp_dbg_cfg() +static void ap_slp_cp_dbg_cfg(void) { *((volatile unsigned int *)(REG_AP_AHB_MCU_PAUSE)) |= BIT_MCU_SLEEP_FOLLOW_CA7_EN; //when ap sleep, cp can continue debug } -static void ap_cpll_rel_cfg() +static void ap_cpll_rel_cfg(void) { *((volatile unsigned int *)(REG_PMU_APB_CPLL_REL_CFG)) |= BIT_CPLL_AP_SEL; } -static void bb_bg_auto_en() -{ - *((volatile unsigned int *)(REG_AON_APB_RES_REG0)) |= 1<<8; -} - - -static void ap_close_wpll_en() +#if 0 +static void ap_close_wpll_en(void) { *((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_WPLL_AP_EN; } -static void ap_close_cpll_en() +static void ap_close_cpll_en(void) { *((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_CPLL_AP_EN; } -static void ap_close_wifipll_en() +static void ap_close_wifipll_en(void) { *((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_WIFIPLL1_AP_EN; } +#endif +#ifndef CONFIG_SPX30G +static void bb_bg_auto_en(void) +{ + *((volatile unsigned int *)(REG_AON_APB_RES_REG0)) |= 1<<8; +} -static void bb_ldo_auto_en() +static void bb_ldo_auto_en(void) { *((volatile unsigned int *)(REG_AON_APB_RES_REG0)) |= 1<<9; -} +} +#endif #ifdef CONFIG_PBINT_7S_RESET_V1 @@ -407,7 +412,9 @@ static void vbat_crash_vol_set(void) void pmic_init(void) { +#ifndef CONFIG_TIZEN u32 val; +#endif pbint_7s_rst_cfg(CONFIG_7S_RST_MODULE_EN, CONFIG_7S_RST_SW_MODE, CONFIG_7S_RST_SHORT_MODE); @@ -458,12 +465,12 @@ int tizen_reboot_recovery_check(void) #endif #define REG32(x) (*((volatile uint32 *)(x))) -void gpu_clk_auto_gate_disable() +void gpu_clk_auto_gate_disable(void) { REG32(REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN) &= ~(0x7F); } -void misc_init() +void misc_init(void) { scx35_pmu_reconfig(); ap_slp_cp_dbg_cfg(); @@ -505,11 +512,11 @@ typedef struct mem_cs_info }mem_cs_info_t; PUBLIC int get_dram_cs_number(void) { - mem_cs_info_t *cs_info_ptr = 0x1C00; + mem_cs_info_t *cs_info_ptr = (mem_cs_info_t *)0x1C00; return cs_info_ptr->cs_number; } PUBLIC int get_dram_cs0_size(void) { - mem_cs_info_t *cs_info_ptr = 0x1C00; + mem_cs_info_t *cs_info_ptr = (mem_cs_info_t *)0x1C00; return cs_info_ptr->cs0_size; } diff --git a/arch/arm/cpu/armv7/sc8830/otp-helper.c b/arch/arm/cpu/armv7/sc8830/otp-helper.c index f98db8c..9c2a64e 100644 --- a/arch/arm/cpu/armv7/sc8830/otp-helper.c +++ b/arch/arm/cpu/armv7/sc8830/otp-helper.c @@ -35,6 +35,9 @@ #define VOL_P1 4200 #define ADC_DATA_OFFSET 128 +extern int __ddie_efuse_prog(int blk_index, u32 val); +extern u32 __adie_efuse_read(int blk_index); + u32 efuse_read(int id,int blk_index) { return __ddie_efuse_read(blk_index); diff --git a/arch/arm/cpu/armv7/sc8830/watchdog.c b/arch/arm/cpu/armv7/sc8830/watchdog.c index e4de885..5e7bf39 100644 --- a/arch/arm/cpu/armv7/sc8830/watchdog.c +++ b/arch/arm/cpu/armv7/sc8830/watchdog.c @@ -2,8 +2,16 @@ #include #include #include +#include #include +extern void WDG_ClockOn(void); +extern void WDG_ResetMCU(void); +extern void WDG_TimerInit(void); +extern void WDG_TimerStop(void); +extern void WDG_TimerLoad(uint32 time_ms); +extern uint32 WDG_PHY_RST_INT_ON(void); + void start_watchdog(uint32_t init_time_ms) { WDG_ClockOn(); diff --git a/arch/arm/cpu/armv7/sc8830/watchdog_hal.c b/arch/arm/cpu/armv7/sc8830/watchdog_hal.c index 8a0629c..c232703 100644 --- a/arch/arm/cpu/armv7/sc8830/watchdog_hal.c +++ b/arch/arm/cpu/armv7/sc8830/watchdog_hal.c @@ -19,6 +19,7 @@ /**---------------------------------------------------------------------------* ** Dependencies * **---------------------------------------------------------------------------*/ +#include #include #include #include @@ -44,7 +45,6 @@ PUBLIC void WDG_TimerStop ) { WDG_CONFIG_T config; - int32 ret; WDG_TRACE ("Watch Dog Trace: WDG_TimerStop"); WDG_PHY_INT_CLR(); @@ -53,7 +53,7 @@ PUBLIC void WDG_TimerStop config.mode = WDG_TIMEOUT_MODE_RESET; config.val = WDG_MAX_COUNT; - ret = WDG_PHY_CONFIG (&config); + WDG_PHY_CONFIG (&config); return; } @@ -70,7 +70,6 @@ PUBLIC void WDG_TimerStart ) { WDG_CONFIG_T config; - int32 ret; WDG_TRACE ("Watch Dog Trace: WDG_TimerStart"); @@ -78,7 +77,7 @@ PUBLIC void WDG_TimerStart config.mode = WDG_TIMEOUT_MODE_RESET; config.val = init_val; - ret = WDG_PHY_CONFIG (&config); + WDG_PHY_CONFIG (&config); } @@ -100,8 +99,6 @@ PUBLIC void WDG_TimerHandler (uint32 int_num) PUBLIC void WDG_TimerInit (void) { WDG_CONFIG_T config; - uint32 status; - int32 ret; WDG_TRACE ("Watch Dog Trace: WDG_TimerInit"); @@ -109,7 +106,7 @@ PUBLIC void WDG_TimerInit (void) config.mode = WDG_TIMEOUT_MODE_RESET; config.val = WDG_INIT_COUNT; - ret = WDG_PHY_CONFIG (&config); + WDG_PHY_CONFIG (&config); } /*****************************************************************************/ @@ -120,14 +117,13 @@ PUBLIC void WDG_TimerInit (void) PUBLIC void WDG_ResetMCU (void) { WDG_CONFIG_T config; - int32 ret; WDG_TRACE ("Watch Dog Trace: WDG_ResetMCU"); config.state = WDG_TIMER_STATE_START ; config.mode = WDG_TIMEOUT_MODE_RESET; config.val = 0x50; - ret = WDG_PHY_CONFIG (&config); + WDG_PHY_CONFIG (&config); } /*****************************************************************************/ @@ -138,15 +134,14 @@ PUBLIC void WDG_ResetMCU (void) PUBLIC void WDG_TimerLoad (uint32 time_ms) { WDG_CONFIG_T config; - int32 ret; - WDG_TRACE ("Watch Dog Trace: WDG_TimerLoad %d", time_ms); + WDG_TRACE ("Watch Dog Trace: WDG_TimerLoad %lu", time_ms); config.state = WDG_TIMER_STATE_KEEP ; config.mode = WDG_TIMEOUT_MODE_KEEP ; config.val = (time_ms * 1000) / 30; - ret = WDG_PHY_CONFIG (&config); + WDG_PHY_CONFIG (&config); } PUBLIC uint32 WDG_PHY_RST_INT_ON(void) @@ -154,7 +149,7 @@ PUBLIC uint32 WDG_PHY_RST_INT_ON(void) uint32 ret = 0; uint32 val = 0; val = WDG_PHY_RST_RAW_INT(); - printf("hw watchdog int raw status 0x%x\n", val); + printf("hw watchdog int raw status 0x%lx\n", val); ret = val & WDG_INT_RST_BIT; WDG_PHY_INT_CLR(); return ret; diff --git a/arch/arm/cpu/armv7/sc8830/watchdog_phy_v3.c b/arch/arm/cpu/armv7/sc8830/watchdog_phy_v3.c index 9b843ec..35c2a88 100644 --- a/arch/arm/cpu/armv7/sc8830/watchdog_phy_v3.c +++ b/arch/arm/cpu/armv7/sc8830/watchdog_phy_v3.c @@ -16,6 +16,7 @@ /**---------------------------------------------------------------------------* ** Dependencies * **---------------------------------------------------------------------------*/ +#include #include #include #include @@ -37,7 +38,7 @@ extern "C" uint32 cnt = 0;\ while((ANA_REG_GET(WDG_INT_RAW) & WDG_LD_BUSY_BIT) && ( cnt < ANA_WDG_LOAD_TIMEOUT_NUM )) cnt++;\ ANA_REG_SET( WDG_LOAD_HIGH, (uint16)(((value) >> 16 ) & 0xffff));\ - ANA_REG_SET( WDG_LOAD_LOW , (uint16)((value) & 0xffff) );\ + ANA_REG_SET( WDG_LOAD_LOW , (uint16)((value) & 0xffff) );\ }while(0) #define CLEAR_WDG_INT(msk) \ @@ -61,9 +62,6 @@ extern "C" /*****************************************************************************/ PUBLIC int32 WDG_PHY_CONFIG (WDG_CONFIG_T *cfg) { - uint32 ctrl = 0; - uint32 val = 0; - ///WDG_TRACE("Watch Dog Trace: Watch Dog Value 0x%8.8x", CHIP_REG_GET(WDG_VALUE)); ANA_REG_SET (WDG_LOCK, WDG_UNLOCK_KEY); diff --git a/arch/arm/include/asm/arch-sc8830/boot_drvapi.h b/arch/arm/include/asm/arch-sc8830/boot_drvapi.h index 5eff94c..7f0836b 100644 --- a/arch/arm/include/asm/arch-sc8830/boot_drvapi.h +++ b/arch/arm/include/asm/arch-sc8830/boot_drvapi.h @@ -76,7 +76,7 @@ PUBLIC uint32 BOOT_GetResetFlag (WDG_HW_FLAG_T type); // Author: Jeff.Li // Note: /*****************************************************************************/ -PUBLIC void BOOT_ResetHWFlag (); +PUBLIC void BOOT_ResetHWFlag (void); /*****************************************************************************/ // Description: Get HW Flag diff --git a/arch/arm/include/asm/arch-sc8830/gpio_phy.h b/arch/arm/include/asm/arch-sc8830/gpio_phy.h index 6a3bbc1..4e6495a 100644 --- a/arch/arm/include/asm/arch-sc8830/gpio_phy.h +++ b/arch/arm/include/asm/arch-sc8830/gpio_phy.h @@ -9,6 +9,13 @@ #include #define GPIO_DBG(fmt...) printf(fmt) +#ifndef WARN +#define WARN(nmu, fmt...) printf(fmt) +#endif + +void __raw_bits_and(unsigned int v, unsigned int a); +void __raw_bits_or(unsigned int v, unsigned int a); + enum gpio_section_type { GPIO_SECTION_GPI = 0x0, GPIO_SECTION_GPO, -- 2.34.1