From 2b3f551ed8038bae0215b54ac0c8989601d094ce Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 25 Feb 2023 16:00:50 -0500 Subject: [PATCH] ac/nir: don't use load_esgs_vertex_stride_amd on gfx6-8 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit An improvement for 9f1e6d8f70a8fa2c174e0070c4331f5f178e6f1. Reviewed-by: Samuel Pitoiset Reviewed-by: Timur Kristóf Part-of: --- src/amd/common/ac_nir_lower_esgs_io_to_mem.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_lower_esgs_io_to_mem.c b/src/amd/common/ac_nir_lower_esgs_io_to_mem.c index e464666..3208eeb 100644 --- a/src/amd/common/ac_nir_lower_esgs_io_to_mem.c +++ b/src/amd/common/ac_nir_lower_esgs_io_to_mem.c @@ -269,7 +269,11 @@ gs_per_vertex_input_offset(nir_builder *b, ? gs_per_vertex_input_vertex_offset_gfx9(b, st, vertex_src) : gs_per_vertex_input_vertex_offset_gfx6(b, st, vertex_src); - vertex_offset = nir_imul(b, vertex_offset, nir_load_esgs_vertex_stride_amd(b)); + /* Gfx6-8 can't emulate VGT_ESGS_RING_ITEMSIZE because it uses the register to determine + * the allocation size of the ESGS ring buffer in memory. + */ + if (st->gfx_level >= GFX9) + vertex_offset = nir_imul(b, vertex_offset, nir_load_esgs_vertex_stride_amd(b)); unsigned base_stride = st->gfx_level >= GFX9 ? 1 : 64 /* Wave size on GFX6-8 */; nir_ssa_def *io_off = ac_nir_calc_io_offset(b, instr, nir_imm_int(b, base_stride * 4u), base_stride, st->map_io); -- 2.7.4