From 2b28c9e0fe97fa2bae2ab52540a2970c0d3bdf8d Mon Sep 17 00:00:00 2001 From: Tianfei zhang Date: Mon, 18 Apr 2022 23:29:42 -0400 Subject: [PATCH] Documentation: fpga: dfl: add link address of feature id table This patch adds the link address of feature id table in documentation. Signed-off-by: Tianfei zhang Reviewed-by: Matthew Gerlach Acked-by: Moritz Fischer Acked-by: Wu Hao Link: https://lore.kernel.org/r/20220419032942.427429-3-tianfei.zhang@intel.com Signed-off-by: Xu Yilun --- Documentation/fpga/dfl.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index ef9eec7..15b6709 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver with matched feature id. FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) could be a reference. +Please refer to below link to existing feature id table and guide for new feature +ids application. +https://github.com/OPAE/dfl-feature-id + + Location of DFLs on a PCI Device ================================ The original method for finding a DFL on a PCI device assumed the start of the -- 2.7.4