From 2ad6f5ff769414a01603f7dcef6a967c8580c372 Mon Sep 17 00:00:00 2001 From: Hang Cheng Date: Sat, 29 Jun 2019 20:37:52 +0800 Subject: [PATCH] hdmitx: correct vid pll div shift preset length [1/3] PD#SWPL-9589 Problem: shift preset length of vid pll div is wrong Solution: modify shift preset length of vid pll div Verify: gxl-p281 Change-Id: Iac897db9d9a36e26df40e8c1ed303e02bddeb92f Signed-off-by: Hang Cheng --- drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c index 1decb1e..f56e3cd 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c @@ -688,11 +688,11 @@ static void set_hpll_od3_clk_div(int div_sel) hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 18, 1); hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 16, 2); hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1); - hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 14); + hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 15); hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_sel, 16, 2); hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 15, 1); - hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 14); + hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 15); hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1); } /* Enable the final output clock */ -- 2.7.4