From 2aac00e4a685525bd7c09bc71522f5a56adf4613 Mon Sep 17 00:00:00 2001
From: "Chenbing.Zheng" <Chenbing.Zheng@streamcomputing.com>
Date: Thu, 24 Feb 2022 05:23:25 +0000
Subject: [PATCH] [RISCV] Add more tests for vcpop and vfirst with VL=0

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D120300
---
 llvm/test/CodeGen/RISCV/rvv/vcpop.ll  | 31 +++++++++++++++++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vfirst.ll | 31 +++++++++++++++++++++++++++++++
 2 files changed, 62 insertions(+)

diff --git a/llvm/test/CodeGen/RISCV/rvv/vcpop.ll b/llvm/test/CodeGen/RISCV/rvv/vcpop.ll
index 1b77ec8d..2006481 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vcpop.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vcpop.ll
@@ -21,6 +21,20 @@ entry:
   ret iXLen %a
 }
 
+define iXLen @intrinsic_vcpop_m_nxv1i1_zero(<vscale x 1 x i1> %0) nounwind {
+; CHECK-LABEL: intrinsic_vcpop_m_nxv1i1_zero:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 0, e8, mf8, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    ret
+entry:
+  %a = call iXLen @llvm.riscv.vcpop.iXLen.nxv1i1(
+    <vscale x 1 x i1> %0,
+    iXLen 0)
+
+  ret iXLen %a
+}
+
 declare iXLen @llvm.riscv.vcpop.mask.iXLen.nxv1i1(
   <vscale x 1 x i1>,
   <vscale x 1 x i1>,
@@ -43,6 +57,23 @@ entry:
   ret iXLen %a
 }
 
+define iXLen @intrinsic_vcpop_mask_m_nxv1i1_zero(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {
+; CHECK-LABEL: intrinsic_vcpop_mask_m_nxv1i1_zero:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v9, v0
+; CHECK-NEXT:    vsetivli zero, 0, e8, mf8, ta, mu
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vcpop.m a0, v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call iXLen @llvm.riscv.vcpop.mask.iXLen.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    iXLen 0)
+
+  ret iXLen %a
+}
+
 declare iXLen @llvm.riscv.vcpop.iXLen.nxv2i1(
   <vscale x 2 x i1>,
   iXLen);
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfirst.ll b/llvm/test/CodeGen/RISCV/rvv/vfirst.ll
index 5d71c17..f42abf7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfirst.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfirst.ll
@@ -21,6 +21,20 @@ entry:
   ret iXLen %a
 }
 
+define iXLen @intrinsic_vfirst_m_nxv1i1_zero(<vscale x 1 x i1> %0) nounwind {
+; CHECK-LABEL: intrinsic_vfirst_m_nxv1i1_zero:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 0, e8, mf8, ta, mu
+; CHECK-NEXT:    vfirst.m a0, v0
+; CHECK-NEXT:    ret
+entry:
+  %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv1i1(
+    <vscale x 1 x i1> %0,
+    iXLen 0)
+
+  ret iXLen %a
+}
+
 declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1(
   <vscale x 1 x i1>,
   <vscale x 1 x i1>,
@@ -43,6 +57,23 @@ entry:
   ret iXLen %a
 }
 
+define iXLen @intrinsic_vfirst_mask_m_nxv1i1_zero(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {
+; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv1i1_zero:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v9, v0
+; CHECK-NEXT:    vsetivli zero, 0, e8, mf8, ta, mu
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vfirst.m a0, v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    iXLen 0)
+
+  ret iXLen %a
+}
+
 declare iXLen @llvm.riscv.vfirst.iXLen.nxv2i1(
   <vscale x 2 x i1>,
   iXLen);
-- 
2.7.4