From 2a64598ef2ec4841dd48483dc368da034d80d933 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 31 Jan 2019 01:38:47 +0000 Subject: [PATCH] GlobalISel: Fix creating MMOs with align 0 llvm-svn: 352712 --- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 6 +- llvm/lib/CodeGen/MachineOperand.cpp | 2 +- llvm/lib/Target/AArch64/AArch64CallLowering.cpp | 5 +- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 4 +- llvm/lib/Target/ARM/ARMCallLowering.cpp | 6 +- llvm/lib/Target/Mips/MipsCallLowering.cpp | 16 ++- llvm/lib/Target/X86/X86CallLowering.cpp | 4 +- .../AArch64/GlobalISel/arm64-callingconv-ios.ll | 10 +- .../AArch64/GlobalISel/call-translator-cse.ll | 4 +- .../AArch64/GlobalISel/call-translator-ios.ll | 16 +-- .../CodeGen/AArch64/GlobalISel/call-translator.ll | 22 ++-- .../AArch64/GlobalISel/varargs-ios-translator.ll | 2 +- llvm/test/CodeGen/AArch64/GlobalISel/vastart.ll | 4 +- .../CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir | 6 +- .../Mips/GlobalISel/irtranslator/extend_args.ll | 24 ++-- .../Mips/GlobalISel/irtranslator/pointers.ll | 2 +- .../Mips/GlobalISel/irtranslator/split_args.ll | 14 +- .../Mips/GlobalISel/irtranslator/stack_args.ll | 4 +- .../X86/GlobalISel/irtranslator-callingconv.ll | 146 ++++++++++----------- 19 files changed, 154 insertions(+), 143 deletions(-) diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 9d3a265..49a2262 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -868,10 +868,11 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, Value *Ptr = CI.getArgOperand(0); unsigned ListSize = TLI.getVaListSizeInBits(*DL) / 8; + // FIXME: Get alignment MIRBuilder.buildInstr(TargetOpcode::G_VASTART) .addUse(getOrCreateVReg(*Ptr)) .addMemOperand(MF->getMachineMemOperand( - MachinePointerInfo(Ptr), MachineMemOperand::MOStore, ListSize, 0)); + MachinePointerInfo(Ptr), MachineMemOperand::MOStore, ListSize, 1)); return true; } case Intrinsic::dbg_value: { @@ -1213,6 +1214,9 @@ bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) { // TODO: Add a GlobalISel version of getTgtMemIntrinsic. if (TLI.getTgtMemIntrinsic(Info, CI, *MF, ID)) { uint64_t Size = Info.memVT.getStoreSize(); + if (Info.align == 0) + Info.align = Size; + MIB.addMemOperand(MF->getMachineMemOperand(MachinePointerInfo(Info.ptrVal), Info.flags, Size, Info.align)); } diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp index ac0fe3006..3ff7a3c 100644 --- a/llvm/lib/CodeGen/MachineOperand.cpp +++ b/llvm/lib/CodeGen/MachineOperand.cpp @@ -993,7 +993,7 @@ MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f, assert((PtrInfo.V.isNull() || PtrInfo.V.is() || isa(PtrInfo.V.get()->getType())) && "invalid pointer value"); - assert(getBaseAlignment() == a && "Alignment is not a power of 2!"); + assert(getBaseAlignment() == a && a != 0 && "Alignment is not a power of 2!"); assert((isLoad() || isStore()) && "Not a load/store!"); AtomicInfo.SSID = static_cast(SSID); diff --git a/llvm/lib/Target/AArch64/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp index 6f412a3..7f8cb7f 100644 --- a/llvm/lib/Target/AArch64/AArch64CallLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp @@ -85,9 +85,10 @@ struct IncomingArgHandler : public CallLowering::ValueHandler { void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size, MachinePointerInfo &MPO, CCValAssign &VA) override { + // FIXME: Get alignment auto MMO = MIRBuilder.getMF().getMachineMemOperand( MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size, - 0); + 1); MIRBuilder.buildLoad(ValVReg, Addr, *MMO); } @@ -161,7 +162,7 @@ struct OutgoingArgHandler : public CallLowering::ValueHandler { .getReg(); } auto MMO = MIRBuilder.getMF().getMachineMemOperand( - MPO, MachineMemOperand::MOStore, Size, 0); + MPO, MachineMemOperand::MOStore, Size, 1); MIRBuilder.buildStore(ValVReg, Addr, *MMO); } diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index b574997..175e2bd 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -420,7 +420,7 @@ void SIFrameLowering::emitEntryFunctionScratchSetup(const GCNSubtarget &ST, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant | MachineMemOperand::MODereferenceable, - 0, 0); + 16, 4); unsigned Offset = Fn.getCallingConv() == CallingConv::AMDGPU_CS ? 16 : 0; BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg) .addReg(Rsrc01) @@ -461,7 +461,7 @@ void SIFrameLowering::emitEntryFunctionScratchSetup(const GCNSubtarget &ST, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant | MachineMemOperand::MODereferenceable, - 0, 0); + 8, 4); BuildMI(MBB, I, DL, LoadDwordX2, Rsrc01) .addReg(MFI->getImplicitBufferPtrUserSGPR()) .addImm(0) // offset diff --git a/llvm/lib/Target/ARM/ARMCallLowering.cpp b/llvm/lib/Target/ARM/ARMCallLowering.cpp index ccb3596..def7c5c 100644 --- a/llvm/lib/Target/ARM/ARMCallLowering.cpp +++ b/llvm/lib/Target/ARM/ARMCallLowering.cpp @@ -131,7 +131,7 @@ struct OutgoingValueHandler : public CallLowering::ValueHandler { unsigned ExtReg = extendRegister(ValVReg, VA); auto MMO = MIRBuilder.getMF().getMachineMemOperand( MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(), - /* Alignment */ 0); + /* Alignment */ 1); MIRBuilder.buildStore(ExtReg, Addr, *MMO); } @@ -331,11 +331,11 @@ struct IncomingValueHandler : public CallLowering::ValueHandler { assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm"); auto LoadVReg = MRI.createGenericVirtualRegister(LLT::scalar(32)); - buildLoad(LoadVReg, Addr, Size, /* Alignment */ 0, MPO); + buildLoad(LoadVReg, Addr, Size, /* Alignment */ 1, MPO); MIRBuilder.buildTrunc(ValVReg, LoadVReg); } else { // If the value is not extended, a simple load will suffice. - buildLoad(ValVReg, Addr, Size, /* Alignment */ 0, MPO); + buildLoad(ValVReg, Addr, Size, /* Alignment */ 1, MPO); } } diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp index 4da88b3..fd0f7921 100644 --- a/llvm/lib/Target/Mips/MipsCallLowering.cpp +++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp @@ -146,15 +146,18 @@ void IncomingValueHandler::assignValueToReg(unsigned ValVReg, unsigned IncomingValueHandler::getStackAddress(const CCValAssign &VA, MachineMemOperand *&MMO) { + MachineFunction &MF = MIRBuilder.getMF(); unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8; unsigned Offset = VA.getLocMemOffset(); - MachineFrameInfo &MFI = MIRBuilder.getMF().getFrameInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); int FI = MFI.CreateFixedObject(Size, Offset, true); MachinePointerInfo MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI); - MMO = MIRBuilder.getMF().getMachineMemOperand(MPO, MachineMemOperand::MOLoad, - Size, /* Alignment */ 0); + + const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering(); + unsigned Align = MinAlign(TFL->getStackAlignment(), Offset); + MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size, Align); unsigned AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32)); MIRBuilder.buildFrameIndex(AddrReg, FI); @@ -220,6 +223,9 @@ void OutgoingValueHandler::assignValueToReg(unsigned ValVReg, unsigned OutgoingValueHandler::getStackAddress(const CCValAssign &VA, MachineMemOperand *&MMO) { + MachineFunction &MF = MIRBuilder.getMF(); + const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering(); + LLT p0 = LLT::pointer(0, 32); LLT s32 = LLT::scalar(32); unsigned SPReg = MRI.createGenericVirtualRegister(p0); @@ -235,8 +241,8 @@ unsigned OutgoingValueHandler::getStackAddress(const CCValAssign &VA, MachinePointerInfo MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset); unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8; - MMO = MIRBuilder.getMF().getMachineMemOperand(MPO, MachineMemOperand::MOStore, - Size, /* Alignment */ 0); + unsigned Align = MinAlign(TFL->getStackAlignment(), Offset); + MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, Size, Align); return AddrReg; } diff --git a/llvm/lib/Target/X86/X86CallLowering.cpp b/llvm/lib/Target/X86/X86CallLowering.cpp index 3a2e328..048e4ca 100644 --- a/llvm/lib/Target/X86/X86CallLowering.cpp +++ b/llvm/lib/Target/X86/X86CallLowering.cpp @@ -148,7 +148,7 @@ struct OutgoingValueHandler : public CallLowering::ValueHandler { unsigned ExtReg = extendRegister(ValVReg, VA); auto MMO = MIRBuilder.getMF().getMachineMemOperand( MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(), - /* Alignment */ 0); + /* Alignment */ 1); MIRBuilder.buildStore(ExtReg, Addr, *MMO); } @@ -244,7 +244,7 @@ struct IncomingValueHandler : public CallLowering::ValueHandler { MachinePointerInfo &MPO, CCValAssign &VA) override { auto MMO = MIRBuilder.getMF().getMachineMemOperand( MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size, - 0); + 1); MIRBuilder.buildLoad(ValVReg, Addr, *MMO); } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll index 256bcf2..f06cd14 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll @@ -17,13 +17,13 @@ target triple = "aarch64-apple-ios9.0" ; CHECK: $d0 = COPY [[D_ONE]] ; CHECK: $x1 = COPY [[TWELVE]] ; CHECK: [[THREE_EXT:%[0-9]+]]:_(s64) = G_ANYEXT [[THREE]] -; CHECK: G_STORE [[THREE_EXT]](s64), {{%[0-9]+}}(p0) :: (store 8 into stack, align 0) +; CHECK: G_STORE [[THREE_EXT]](s64), {{%[0-9]+}}(p0) :: (store 8 into stack, align 1) ; CHECK: [[ONE_EXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ONE]] -; CHECK: G_STORE [[ONE_EXT]](s64), {{%[0-9]+}}(p0) :: (store 8 into stack + 8, align 0) +; CHECK: G_STORE [[ONE_EXT]](s64), {{%[0-9]+}}(p0) :: (store 8 into stack + 8, align 1) ; CHECK: [[FOUR_EXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FOUR]] -; CHECK: G_STORE [[FOUR_EXT]](s64), {{%[0-9]+}}(p0) :: (store 8 into stack + 16, align 0) -; CHECK: G_STORE [[F_ONE]](s32), {{%[0-9]+}}(p0) :: (store 4 into stack + 24, align 0) -; CHECK: G_STORE [[TWO]](s64), {{%[0-9]+}}(p0) :: (store 8 into stack + 32, align 0) +; CHECK: G_STORE [[FOUR_EXT]](s64), {{%[0-9]+}}(p0) :: (store 8 into stack + 16, align 1) +; CHECK: G_STORE [[F_ONE]](s32), {{%[0-9]+}}(p0) :: (store 4 into stack + 24, align 1) +; CHECK: G_STORE [[TWO]](s64), {{%[0-9]+}}(p0) :: (store 8 into stack + 32, align 1) declare void @varargs(i32, double, i64, ...) define void @test_varargs() { call void(i32, double, i64, ...) @varargs(i32 42, double 1.0, i64 12, i8 3, i16 1, i32 4, float 1.0, double 2.0) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll index 7995d1a..9120c10 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll @@ -16,11 +16,11 @@ ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST2]](s64) -; CHECK: G_STORE [[EXTLO]](s64), [[GEP2]](p0) :: (store 8 into stack, align 0) +; CHECK: G_STORE [[EXTLO]](s64), [[GEP2]](p0) :: (store 8 into stack, align 1) ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[CST3:%[0-9]+]]:_(s64) = COPY [[CST]] ; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST3]](s64) -; CHECK: G_STORE [[EXTHI]](s64), [[GEP3]](p0) :: (store 8 into stack + 8, align 0) +; CHECK: G_STORE [[EXTHI]](s64), [[GEP3]](p0) :: (store 8 into stack + 8, align 1) define void @test_split_struct([2 x i64]* %ptr) { %struct = load [2 x i64], [2 x i64]* %ptr call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3, diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll index 1cb2e9a..429c08b 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll @@ -6,9 +6,9 @@ ; CHECK-DAG: - { id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1, ; CHECK-DAG: - { id: [[STACK8:[0-9]+]], type: default, offset: 1, size: 1, ; CHECK: [[LHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] -; CHECK: [[LHS:%[0-9]+]]:_(s8) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0) +; CHECK: [[LHS:%[0-9]+]]:_(s8) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]]) ; CHECK: [[RHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]] -; CHECK: [[RHS:%[0-9]+]]:_(s8) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0) +; CHECK: [[RHS:%[0-9]+]]:_(s8) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]]) ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[LHS]], [[RHS]] ; CHECK: [[SUM32:%[0-9]+]]:_(s32) = G_SEXT [[SUM]](s8) ; CHECK: $w0 = COPY [[SUM32]](s32) @@ -23,11 +23,11 @@ define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs) ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[C42_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C42_OFFS]](s64) -; CHECK: G_STORE [[C42]](s8), [[C42_LOC]](p0) :: (store 1 into stack, align 0) +; CHECK: G_STORE [[C42]](s8), [[C42_LOC]](p0) :: (store 1 into stack) ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[C12_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C12_OFFS]](s64) -; CHECK: G_STORE [[C12]](s8), [[C12_LOC]](p0) :: (store 1 into stack + 1, align 0) +; CHECK: G_STORE [[C12]](s8), [[C12_LOC]](p0) :: (store 1 into stack + 1) ; CHECK: BL @test_stack_slots define void @test_call_stack() { call signext i8 @test_stack_slots([8 x i64] undef, i8 signext 42, i8 signext 12) @@ -68,12 +68,12 @@ define void @take_128bit_struct([2 x i64]* %ptr, [2 x i64] %in) { ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]](s64) -; CHECK: G_STORE [[EXT1]](s64), [[ADDR]](p0) :: (store 8 into stack, align 0) +; CHECK: G_STORE [[EXT1]](s64), [[ADDR]](p0) :: (store 8 into stack, align 1) ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]] -; CHECK: G_STORE [[EXT2]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 0) +; CHECK: G_STORE [[EXT2]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 1) define void @test_split_struct([2 x i64]* %ptr) { %struct = load [2 x i64], [2 x i64]* %ptr call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3, @@ -88,10 +88,10 @@ define void @test_split_struct([2 x i64]* %ptr) { ; CHECK-DAG: - { id: [[HI_FRAME:[0-9]+]], type: default, offset: 8, size: 8 ; CHECK: [[LOPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LO_FRAME]] -; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD [[LOPTR]](p0) :: (invariant load 8 from %fixed-stack.[[LO_FRAME]], align 0) +; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD [[LOPTR]](p0) :: (invariant load 8 from %fixed-stack.[[LO_FRAME]], align 1) ; CHECK: [[HIPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[HI_FRAME]] -; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[HIPTR]](p0) :: (invariant load 8 from %fixed-stack.[[HI_FRAME]], align 0) +; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[HIPTR]](p0) :: (invariant load 8 from %fixed-stack.[[HI_FRAME]], align 1) define void @take_split_struct([2 x i64]* %ptr, i64, i64, i64, i64, i64, i64, [2 x i64] %in) { diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll index e3995b2..9072873 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll @@ -196,11 +196,11 @@ define zeroext i8 @test_abi_zext_ret(i8* %addr) { ; CHECK-DAG: - { id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 8, ; CHECK-DAG: - { id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 8, ; CHECK: [[LHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] -; CHECK: [[LHS:%[0-9]+]]:_(s64) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0) +; CHECK: [[LHS:%[0-9]+]]:_(s64) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 1) ; CHECK: [[RHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]] -; CHECK: [[RHS:%[0-9]+]]:_(s64) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 0) +; CHECK: [[RHS:%[0-9]+]]:_(s64) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 1) ; CHECK: [[ADDR_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]] -; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_LOAD [[ADDR_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK16]], align 0) +; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_LOAD [[ADDR_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK16]], align 1) ; CHECK: [[SUM:%[0-9]+]]:_(s64) = G_ADD [[LHS]], [[RHS]] ; CHECK: G_STORE [[SUM]](s64), [[ADDR]](p0) define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, i64* %addr) { @@ -218,15 +218,15 @@ define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, i64* %addr) { ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[C42_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C42_OFFS]](s64) -; CHECK: G_STORE [[C42]](s64), [[C42_LOC]](p0) :: (store 8 into stack, align 0) +; CHECK: G_STORE [[C42]](s64), [[C42_LOC]](p0) :: (store 8 into stack, align 1) ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[C12_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C12_OFFS]](s64) -; CHECK: G_STORE [[C12]](s64), [[C12_LOC]](p0) :: (store 8 into stack + 8, align 0) +; CHECK: G_STORE [[C12]](s64), [[C12_LOC]](p0) :: (store 8 into stack + 8, align 1) ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[PTR_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; CHECK: [[PTR_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[PTR_OFFS]](s64) -; CHECK: G_STORE [[PTR]](p0), [[PTR_LOC]](p0) :: (store 8 into stack + 16, align 0) +; CHECK: G_STORE [[PTR]](p0), [[PTR_LOC]](p0) :: (store 8 into stack + 16, align 1) ; CHECK: BL @test_stack_slots ; CHECK: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp define void @test_call_stack() { @@ -239,7 +239,7 @@ define void @test_call_stack() { ; CHECK-NEXT: - { id: [[SLOT:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, stack-id: 0, ; CHECK-NEXT: isImmutable: true, ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[SLOT]] -; CHECK: {{%[0-9]+}}:_(s1) = G_LOAD [[ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[SLOT]], align 0) +; CHECK: {{%[0-9]+}}:_(s1) = G_LOAD [[ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[SLOT]]) define void @test_mem_i1([8 x i64], i1 %in) { ret void } @@ -280,11 +280,11 @@ define void @take_128bit_struct([2 x i64]* %ptr, [2 x i64] %in) { ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST2]](s64) -; CHECK: G_STORE [[EXTLO]](s64), [[GEP2]](p0) :: (store 8 into stack, align 0) +; CHECK: G_STORE [[EXTLO]](s64), [[GEP2]](p0) :: (store 8 into stack, align 1) ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST3]](s64) -; CHECK: G_STORE [[EXTHI]](s64), [[GEP3]](p0) :: (store 8 into stack + 8, align 0) +; CHECK: G_STORE [[EXTHI]](s64), [[GEP3]](p0) :: (store 8 into stack + 8, align 1) define void @test_split_struct([2 x i64]* %ptr) { %struct = load [2 x i64], [2 x i64]* %ptr call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3, @@ -299,10 +299,10 @@ define void @test_split_struct([2 x i64]* %ptr) { ; CHECK-DAG: - { id: [[HI_FRAME:[0-9]+]], type: default, offset: 8, size: 8 ; CHECK: [[LOPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LO_FRAME]] -; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD [[LOPTR]](p0) :: (invariant load 8 from %fixed-stack.[[LO_FRAME]], align 0) +; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD [[LOPTR]](p0) :: (invariant load 8 from %fixed-stack.[[LO_FRAME]], align 1) ; CHECK: [[HIPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[HI_FRAME]] -; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[HIPTR]](p0) :: (invariant load 8 from %fixed-stack.[[HI_FRAME]], align 0) +; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[HIPTR]](p0) :: (invariant load 8 from %fixed-stack.[[HI_FRAME]], align 1) define void @take_split_struct([2 x i64]* %ptr, i64, i64, i64, i64, i64, i64, [2 x i64] %in) { diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll index 770985a..5f861f4 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll @@ -8,7 +8,7 @@ define void @test_varargs_sentinel(i8* %list, i64, i64, i64, i64, i64, i64, i64, ; CHECK: body: ; CHECK: [[LIST:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[VARARGS_AREA:%[0-9]+]]:gpr64common = ADDXri %fixed-stack.[[VARARGS_SLOT]], 0, 0 -; CHECK: STRXui [[VARARGS_AREA]], [[LIST]], 0 :: (store 8 into %ir.list, align 0) +; CHECK: STRXui [[VARARGS_AREA]], [[LIST]], 0 :: (store 8 into %ir.list, align 1) call void @llvm.va_start(i8* %list) ret void } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/vastart.ll b/llvm/test/CodeGen/AArch64/GlobalISel/vastart.ll index 9e83f030..32d1ac7 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/vastart.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/vastart.ll @@ -6,8 +6,8 @@ declare void @llvm.va_start(i8*) define void @test_va_start(i8* %list) { ; CHECK-LABEL: name: test_va_start ; CHECK: [[LIST:%[0-9]+]]:_(p0) = COPY $x0 -; CHECK-IOS: G_VASTART [[LIST]](p0) :: (store 8 into %ir.list, align 0) -; CHECK-LINUX: G_VASTART [[LIST]](p0) :: (store 32 into %ir.list, align 0) +; CHECK-IOS: G_VASTART [[LIST]](p0) :: (store 8 into %ir.list, align 1) +; CHECK-LINUX: G_VASTART [[LIST]](p0) :: (store 32 into %ir.list, align 1) call void @llvm.va_start(i8* %list) ret void } diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir index b9f4095..5ecf9b7 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir @@ -96,11 +96,11 @@ body: | ; SOFT-ABI: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT-ABI: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32) - ; FIXME: This ought to be align 8 but ARM's call lowering hardcodes it to 0 - ; SOFT-ABI: G_STORE [[Y0]](s32), [[FI1]](p0){{.*}}store 4 into stack, align 0) + ; FIXME: This ought to be align 8 but ARM's call lowering hardcodes it to 1 + ; SOFT-ABI: G_STORE [[Y0]](s32), [[FI1]](p0){{.*}}store 4 into stack, align 1) ; SOFT-ABI: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; SOFT-ABI: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[FI1]], [[OFF2]](s32) - ; SOFT-ABI: G_STORE [[Y1]](s32), [[FI2]](p0){{.*}}store 4 into stack + 4) + ; SOFT-ABI: G_STORE [[Y1]](s32), [[FI2]](p0){{.*}}store 4 into stack + 4, align 1) ; SOFT-ABI: BL &fma, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1 ; SOFT-ABI-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT-ABI-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll index f8cf2c2..a1743c4 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll @@ -54,7 +54,7 @@ define signext i8 @call_sext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0) + ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8) ; MIPS32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[LOAD]](s32) ; MIPS32: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp ; MIPS32: $a0 = COPY [[COPY]](s32) @@ -65,7 +65,7 @@ define signext i8 @call_sext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C]](s32) ; MIPS32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s8) - ; MIPS32: G_STORE [[SEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 0) + ; MIPS32: G_STORE [[SEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 8) ; MIPS32: JAL @sext_stack_arg_i8, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0 ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0 ; MIPS32: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY5]](s32) @@ -87,7 +87,7 @@ define zeroext i8 @call_zext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0) + ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8) ; MIPS32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[LOAD]](s32) ; MIPS32: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp ; MIPS32: $a0 = COPY [[COPY]](s32) @@ -98,7 +98,7 @@ define zeroext i8 @call_zext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C]](s32) ; MIPS32: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8) - ; MIPS32: G_STORE [[ZEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 0) + ; MIPS32: G_STORE [[ZEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 8) ; MIPS32: JAL @zext_stack_arg_i8, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0 ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0 ; MIPS32: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY5]](s32) @@ -120,7 +120,7 @@ define i8 @call_aext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8 %a) { ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0) + ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8) ; MIPS32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[LOAD]](s32) ; MIPS32: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp ; MIPS32: $a0 = COPY [[COPY]](s32) @@ -131,7 +131,7 @@ define i8 @call_aext_stack_arg_i8(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i8 %a) { ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C]](s32) ; MIPS32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8) - ; MIPS32: G_STORE [[ANYEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 0) + ; MIPS32: G_STORE [[ANYEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 8) ; MIPS32: JAL @aext_stack_arg_i8, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0 ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0 ; MIPS32: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY5]](s32) @@ -197,7 +197,7 @@ define signext i16 @call_sext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4, ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0) + ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8) ; MIPS32: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32) ; MIPS32: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp ; MIPS32: $a0 = COPY [[COPY]](s32) @@ -208,7 +208,7 @@ define signext i16 @call_sext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4, ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C]](s32) ; MIPS32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16) - ; MIPS32: G_STORE [[SEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 0) + ; MIPS32: G_STORE [[SEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 8) ; MIPS32: JAL @sext_stack_arg_i16, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0 ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0 ; MIPS32: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s32) @@ -230,7 +230,7 @@ define zeroext i16 @call_zext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4, ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0) + ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8) ; MIPS32: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32) ; MIPS32: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp ; MIPS32: $a0 = COPY [[COPY]](s32) @@ -241,7 +241,7 @@ define zeroext i16 @call_zext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4, ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C]](s32) ; MIPS32: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16) - ; MIPS32: G_STORE [[ZEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 0) + ; MIPS32: G_STORE [[ZEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 8) ; MIPS32: JAL @zext_stack_arg_i16, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0 ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0 ; MIPS32: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s32) @@ -263,7 +263,7 @@ define i16 @call_aext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i16 %a) ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0) + ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8) ; MIPS32: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32) ; MIPS32: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp ; MIPS32: $a0 = COPY [[COPY]](s32) @@ -274,7 +274,7 @@ define i16 @call_aext_stack_arg_i16(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i16 %a) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C]](s32) ; MIPS32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) - ; MIPS32: G_STORE [[ANYEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 0) + ; MIPS32: G_STORE [[ANYEXT]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 8) ; MIPS32: JAL @aext_stack_arg_i16, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0 ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0 ; MIPS32: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s32) diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll index 41fe492..0163182 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll @@ -24,7 +24,7 @@ define i32 @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32* %p) { ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; MIPS32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0) + ; MIPS32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8) ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.p) ; MIPS32: $v0 = COPY [[LOAD1]](s32) ; MIPS32: RetRA implicit $v0 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll index 13ffd24..803de00 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll @@ -27,9 +27,9 @@ define i64 @i64_stack(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i64 %a) { ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.[[STACK1]], align 0) + ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.[[STACK1]], align 8) ; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.[[STACK0]], align 0) + ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.[[STACK0]]) ; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32) ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64) ; MIPS32: $v0 = COPY [[UV]](s32) @@ -68,11 +68,11 @@ define i64 @i64_stack_allign(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %s16, i64 % ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 - ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.[[STACK2]], align 0) + ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.[[STACK2]], align 8) ; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.[[STACK1]], align 0) + ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.[[STACK1]], align 8) ; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load 4 from %fixed-stack.[[STACK0]], align 0) + ; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load 4 from %fixed-stack.[[STACK0]]) ; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD1]](s32), [[LOAD2]](s32) ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64) ; MIPS32: $v0 = COPY [[UV]](s32) @@ -93,9 +93,9 @@ define i64 @i64_reg_stack(i32 %a0, i32 %a1, i32 %a2, i64 %a) { ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.[[STACK1]], align 0) + ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.[[STACK1]], align 8) ; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.[[STACK0]], align 0) + ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.[[STACK0]]) ; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32) ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64) ; MIPS32: $v0 = COPY [[UV]](s32) diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll index ae89af4..37d75bc 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll @@ -12,7 +12,7 @@ define i32 @g(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32 %x5){ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0) + ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8) ; MIPS32: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp ; MIPS32: $a0 = COPY [[COPY]](s32) ; MIPS32: $a1 = COPY [[COPY1]](s32) @@ -21,7 +21,7 @@ define i32 @g(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32 %x5){ ; MIPS32: [[COPY4:%[0-9]+]]:_(p0) = COPY $sp ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C]](s32) - ; MIPS32: G_STORE [[LOAD]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 0) + ; MIPS32: G_STORE [[LOAD]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 8) ; MIPS32: JAL @f, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0 ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0 ; MIPS32: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp diff --git a/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll b/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll index 552911e..37cd71f 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll +++ b/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll @@ -10,21 +10,21 @@ define i8 @test_i8_args_8(i8 %arg1, i8 %arg2, i8 %arg3, i8 %arg4, ; X32-LABEL: name: test_i8_args_8 ; X32: bb.1.entry: ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.7 - ; X32: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 1 from %fixed-stack.7, align 0) + ; X32: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 1 from %fixed-stack.7) ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6 - ; X32: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 1 from %fixed-stack.6, align 0) + ; X32: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 1 from %fixed-stack.6) ; X32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5 - ; X32: [[LOAD2:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load 1 from %fixed-stack.5, align 0) + ; X32: [[LOAD2:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load 1 from %fixed-stack.5) ; X32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 - ; X32: [[LOAD3:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load 1 from %fixed-stack.4, align 0) + ; X32: [[LOAD3:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load 1 from %fixed-stack.4) ; X32: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 - ; X32: [[LOAD4:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX4]](p0) :: (invariant load 1 from %fixed-stack.3, align 0) + ; X32: [[LOAD4:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX4]](p0) :: (invariant load 1 from %fixed-stack.3) ; X32: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 - ; X32: [[LOAD5:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX5]](p0) :: (invariant load 1 from %fixed-stack.2, align 0) + ; X32: [[LOAD5:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX5]](p0) :: (invariant load 1 from %fixed-stack.2) ; X32: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; X32: [[LOAD6:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX6]](p0) :: (invariant load 1 from %fixed-stack.1, align 0) + ; X32: [[LOAD6:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX6]](p0) :: (invariant load 1 from %fixed-stack.1) ; X32: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X32: [[LOAD7:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX7]](p0) :: (invariant load 1 from %fixed-stack.0, align 0) + ; X32: [[LOAD7:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX7]](p0) :: (invariant load 1 from %fixed-stack.0) ; X32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a1_8bit ; X32: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a7_8bit ; X32: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a8_8bit @@ -49,9 +49,9 @@ define i8 @test_i8_args_8(i8 %arg1, i8 %arg2, i8 %arg3, i8 %arg4, ; X64: [[COPY5:%[0-9]+]]:_(s32) = COPY $r9d ; X64: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[COPY5]](s32) ; X64: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; X64: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 1 from %fixed-stack.1, align 0) + ; X64: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 1 from %fixed-stack.1) ; X64: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X64: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 1 from %fixed-stack.0, align 0) + ; X64: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 1 from %fixed-stack.0) ; X64: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a1_8bit ; X64: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a7_8bit ; X64: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a8_8bit @@ -76,21 +76,21 @@ define i32 @test_i32_args_8(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, ; X32-LABEL: name: test_i32_args_8 ; X32: bb.1.entry: ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.7 - ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.7, align 0) + ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.7, align 1) ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6 - ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.6, align 0) + ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.6, align 1) ; X32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5 - ; X32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load 4 from %fixed-stack.5, align 0) + ; X32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load 4 from %fixed-stack.5, align 1) ; X32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 - ; X32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load 4 from %fixed-stack.4, align 0) + ; X32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load 4 from %fixed-stack.4, align 1) ; X32: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 - ; X32: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p0) :: (invariant load 4 from %fixed-stack.3, align 0) + ; X32: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p0) :: (invariant load 4 from %fixed-stack.3, align 1) ; X32: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 - ; X32: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p0) :: (invariant load 4 from %fixed-stack.2, align 0) + ; X32: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p0) :: (invariant load 4 from %fixed-stack.2, align 1) ; X32: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; X32: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p0) :: (invariant load 4 from %fixed-stack.1, align 0) + ; X32: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p0) :: (invariant load 4 from %fixed-stack.1, align 1) ; X32: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X32: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p0) :: (invariant load 4 from %fixed-stack.0, align 1) ; X32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a1_32bit ; X32: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a7_32bit ; X32: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a8_32bit @@ -109,9 +109,9 @@ define i32 @test_i32_args_8(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, ; X64: [[COPY4:%[0-9]+]]:_(s32) = COPY $r8d ; X64: [[COPY5:%[0-9]+]]:_(s32) = COPY $r9d ; X64: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; X64: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.1, align 0) + ; X64: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.1, align 1) ; X64: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X64: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X64: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.0, align 1) ; X64: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a1_32bit ; X64: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a7_32bit ; X64: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a8_32bit @@ -136,37 +136,37 @@ define i64 @test_i64_args_8(i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, ; X32-LABEL: name: test_i64_args_8 ; X32: bb.1.entry: ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.15 - ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.15, align 0) + ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.15, align 1) ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.14 - ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.14, align 0) + ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.14, align 1) ; X32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.13 - ; X32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load 4 from %fixed-stack.13, align 0) + ; X32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load 4 from %fixed-stack.13, align 1) ; X32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.12 - ; X32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load 4 from %fixed-stack.12, align 0) + ; X32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load 4 from %fixed-stack.12, align 1) ; X32: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.11 - ; X32: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p0) :: (invariant load 4 from %fixed-stack.11, align 0) + ; X32: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p0) :: (invariant load 4 from %fixed-stack.11, align 1) ; X32: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.10 - ; X32: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p0) :: (invariant load 4 from %fixed-stack.10, align 0) + ; X32: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p0) :: (invariant load 4 from %fixed-stack.10, align 1) ; X32: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.9 - ; X32: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p0) :: (invariant load 4 from %fixed-stack.9, align 0) + ; X32: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p0) :: (invariant load 4 from %fixed-stack.9, align 1) ; X32: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.8 - ; X32: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p0) :: (invariant load 4 from %fixed-stack.8, align 0) + ; X32: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p0) :: (invariant load 4 from %fixed-stack.8, align 1) ; X32: [[FRAME_INDEX8:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.7 - ; X32: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX8]](p0) :: (invariant load 4 from %fixed-stack.7, align 0) + ; X32: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX8]](p0) :: (invariant load 4 from %fixed-stack.7, align 1) ; X32: [[FRAME_INDEX9:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6 - ; X32: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX9]](p0) :: (invariant load 4 from %fixed-stack.6, align 0) + ; X32: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX9]](p0) :: (invariant load 4 from %fixed-stack.6, align 1) ; X32: [[FRAME_INDEX10:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5 - ; X32: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX10]](p0) :: (invariant load 4 from %fixed-stack.5, align 0) + ; X32: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX10]](p0) :: (invariant load 4 from %fixed-stack.5, align 1) ; X32: [[FRAME_INDEX11:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 - ; X32: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX11]](p0) :: (invariant load 4 from %fixed-stack.4, align 0) + ; X32: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX11]](p0) :: (invariant load 4 from %fixed-stack.4, align 1) ; X32: [[FRAME_INDEX12:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 - ; X32: [[LOAD12:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX12]](p0) :: (invariant load 4 from %fixed-stack.3, align 0) + ; X32: [[LOAD12:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX12]](p0) :: (invariant load 4 from %fixed-stack.3, align 1) ; X32: [[FRAME_INDEX13:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 - ; X32: [[LOAD13:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX13]](p0) :: (invariant load 4 from %fixed-stack.2, align 0) + ; X32: [[LOAD13:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX13]](p0) :: (invariant load 4 from %fixed-stack.2, align 1) ; X32: [[FRAME_INDEX14:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; X32: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX14]](p0) :: (invariant load 4 from %fixed-stack.1, align 0) + ; X32: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX14]](p0) :: (invariant load 4 from %fixed-stack.1, align 1) ; X32: [[FRAME_INDEX15:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X32: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX15]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX15]](p0) :: (invariant load 4 from %fixed-stack.0, align 1) ; X32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32) ; X32: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32) ; X32: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD4]](s32), [[LOAD5]](s32) @@ -195,9 +195,9 @@ define i64 @test_i64_args_8(i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, ; X64: [[COPY4:%[0-9]+]]:_(s64) = COPY $r8 ; X64: [[COPY5:%[0-9]+]]:_(s64) = COPY $r9 ; X64: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; X64: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 8 from %fixed-stack.1, align 0) + ; X64: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 8 from %fixed-stack.1, align 1) ; X64: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X64: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 8 from %fixed-stack.0, align 0) + ; X64: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 8 from %fixed-stack.0, align 1) ; X64: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a1_64bit ; X64: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a7_64bit ; X64: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a8_64bit @@ -219,9 +219,9 @@ define float @test_float_args(float %arg1, float %arg2) { ; X32-LABEL: name: test_float_args ; X32: bb.1 (%ir-block.0): ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.1, align 0) + ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.1, align 1) ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.0, align 1) ; X32: [[ANYEXT:%[0-9]+]]:_(s80) = G_ANYEXT [[LOAD1]](s32) ; X32: $fp0 = COPY [[ANYEXT]](s80) ; X32: RET 0, implicit $fp0 @@ -242,9 +242,9 @@ define double @test_double_args(double %arg1, double %arg2) { ; X32-LABEL: name: test_double_args ; X32: bb.1 (%ir-block.0): ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; X32: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 8 from %fixed-stack.1, align 0) + ; X32: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 8 from %fixed-stack.1, align 1) ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X32: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 8 from %fixed-stack.0, align 0) + ; X32: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 8 from %fixed-stack.0, align 1) ; X32: [[ANYEXT:%[0-9]+]]:_(s80) = G_ANYEXT [[LOAD1]](s64) ; X32: $fp0 = COPY [[ANYEXT]](s80) ; X32: RET 0, implicit $fp0 @@ -319,7 +319,7 @@ define i32 * @test_memop_i32(i32 * %p1) { ; X32-LABEL: name: test_memop_i32 ; X32: bb.1 (%ir-block.0): ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 1) ; X32: $eax = COPY [[LOAD]](p0) ; X32: RET 0, implicit $eax ; X64-LABEL: name: test_memop_i32 @@ -354,18 +354,18 @@ define void @test_simple_arg(i32 %in0, i32 %in1) { ; X32-LABEL: name: test_simple_arg ; X32: bb.1 (%ir-block.0): ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.1, align 0) + ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.1, align 1) ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.0, align 1) ; X32: ADJCALLSTACKDOWN32 8, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: [[COPY:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s32) - ; X32: G_STORE [[LOAD1]](s32), [[GEP]](p0) :: (store 4 into stack, align 0) + ; X32: G_STORE [[LOAD1]](s32), [[GEP]](p0) :: (store 4 into stack, align 1) ; X32: [[COPY1:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s32) - ; X32: G_STORE [[LOAD]](s32), [[GEP1]](p0) :: (store 4 into stack + 4, align 0) + ; X32: G_STORE [[LOAD]](s32), [[GEP1]](p0) :: (store 4 into stack + 4, align 1) ; X32: CALLpcrel32 @simple_arg_callee, csr_32, implicit $esp, implicit $ssp ; X32: ADJCALLSTACKUP32 8, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: RET 0 @@ -389,40 +389,40 @@ define void @test_simple_arg8_call(i32 %in0) { ; X32-LABEL: name: test_simple_arg8_call ; X32: bb.1 (%ir-block.0): ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 1) ; X32: ADJCALLSTACKDOWN32 32, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: [[COPY:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s32) - ; X32: G_STORE [[LOAD]](s32), [[GEP]](p0) :: (store 4 into stack, align 0) + ; X32: G_STORE [[LOAD]](s32), [[GEP]](p0) :: (store 4 into stack, align 1) ; X32: [[COPY1:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s32) - ; X32: G_STORE [[LOAD]](s32), [[GEP1]](p0) :: (store 4 into stack + 4, align 0) + ; X32: G_STORE [[LOAD]](s32), [[GEP1]](p0) :: (store 4 into stack + 4, align 1) ; X32: [[COPY2:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; X32: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[COPY2]], [[C2]](s32) - ; X32: G_STORE [[LOAD]](s32), [[GEP2]](p0) :: (store 4 into stack + 8, align 0) + ; X32: G_STORE [[LOAD]](s32), [[GEP2]](p0) :: (store 4 into stack + 8, align 1) ; X32: [[COPY3:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 ; X32: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[COPY3]], [[C3]](s32) - ; X32: G_STORE [[LOAD]](s32), [[GEP3]](p0) :: (store 4 into stack + 12, align 0) + ; X32: G_STORE [[LOAD]](s32), [[GEP3]](p0) :: (store 4 into stack + 12, align 1) ; X32: [[COPY4:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; X32: [[GEP4:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C4]](s32) - ; X32: G_STORE [[LOAD]](s32), [[GEP4]](p0) :: (store 4 into stack + 16, align 0) + ; X32: G_STORE [[LOAD]](s32), [[GEP4]](p0) :: (store 4 into stack + 16, align 1) ; X32: [[COPY5:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20 ; X32: [[GEP5:%[0-9]+]]:_(p0) = G_GEP [[COPY5]], [[C5]](s32) - ; X32: G_STORE [[LOAD]](s32), [[GEP5]](p0) :: (store 4 into stack + 20, align 0) + ; X32: G_STORE [[LOAD]](s32), [[GEP5]](p0) :: (store 4 into stack + 20, align 1) ; X32: [[COPY6:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; X32: [[GEP6:%[0-9]+]]:_(p0) = G_GEP [[COPY6]], [[C6]](s32) - ; X32: G_STORE [[LOAD]](s32), [[GEP6]](p0) :: (store 4 into stack + 24, align 0) + ; X32: G_STORE [[LOAD]](s32), [[GEP6]](p0) :: (store 4 into stack + 24, align 1) ; X32: [[COPY7:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 28 ; X32: [[GEP7:%[0-9]+]]:_(p0) = G_GEP [[COPY7]], [[C7]](s32) - ; X32: G_STORE [[LOAD]](s32), [[GEP7]](p0) :: (store 4 into stack + 28, align 0) + ; X32: G_STORE [[LOAD]](s32), [[GEP7]](p0) :: (store 4 into stack + 28, align 1) ; X32: CALLpcrel32 @simple_arg8_callee, csr_32, implicit $esp, implicit $ssp ; X32: ADJCALLSTACKUP32 32, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: RET 0 @@ -440,11 +440,11 @@ define void @test_simple_arg8_call(i32 %in0) { ; X64: [[COPY1:%[0-9]+]]:_(p0) = COPY $rsp ; X64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; X64: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C]](s64) - ; X64: G_STORE [[COPY]](s32), [[GEP]](p0) :: (store 4 into stack, align 0) + ; X64: G_STORE [[COPY]](s32), [[GEP]](p0) :: (store 4 into stack, align 1) ; X64: [[COPY2:%[0-9]+]]:_(p0) = COPY $rsp ; X64: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; X64: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY2]], [[C1]](s64) - ; X64: G_STORE [[COPY]](s32), [[GEP1]](p0) :: (store 4 into stack + 8, align 0) + ; X64: G_STORE [[COPY]](s32), [[GEP1]](p0) :: (store 4 into stack + 8, align 1) ; X64: CALL64pcrel32 @simple_arg8_callee, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit $edx, implicit $ecx, implicit $r8d, implicit $r9d ; X64: ADJCALLSTACKUP64 16, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp ; X64: RET 0 @@ -461,7 +461,7 @@ define i32 @test_simple_return_callee() { ; X32: [[COPY:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C1]](s32) - ; X32: G_STORE [[C]](s32), [[GEP]](p0) :: (store 4 into stack, align 0) + ; X32: G_STORE [[C]](s32), [[GEP]](p0) :: (store 4 into stack, align 1) ; X32: CALLpcrel32 @simple_return_callee, csr_32, implicit $esp, implicit $ssp, implicit-def $eax ; X32: [[COPY1:%[0-9]+]]:_(s32) = COPY $eax ; X32: ADJCALLSTACKUP32 4, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp @@ -493,7 +493,7 @@ define <8 x i32> @test_split_return_callee(<8 x i32> %arg1, <8 x i32> %arg2) { ; X32: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $xmm1 ; X32: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $xmm2 ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X32: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 16 from %fixed-stack.0, align 0) + ; X32: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 16 from %fixed-stack.0, align 1) ; X32: [[MV:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY]](<4 x s32>), [[COPY1]](<4 x s32>) ; X32: [[MV1:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY2]](<4 x s32>), [[LOAD]](<4 x s32>) ; X32: ADJCALLSTACKDOWN32 0, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp @@ -542,7 +542,7 @@ define void @test_indirect_call(void()* %func) { ; X32-LABEL: name: test_indirect_call ; X32: bb.1 (%ir-block.0): ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X32: [[LOAD:%[0-9]+]]:gr32(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: [[LOAD:%[0-9]+]]:gr32(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 1) ; X32: ADJCALLSTACKDOWN32 0, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: CALL32r [[LOAD]](p0), csr_32, implicit $esp, implicit $ssp ; X32: ADJCALLSTACKUP32 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp @@ -565,14 +565,14 @@ define void @test_abi_exts_call(i8* %addr) { ; X32-LABEL: name: test_abi_exts_call ; X32: bb.1 (%ir-block.0): ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 1) ; X32: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p0) :: (load 1 from %ir.addr) ; X32: ADJCALLSTACKDOWN32 4, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: [[COPY:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s32) ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD1]](s8) - ; X32: G_STORE [[ANYEXT]](s32), [[GEP]](p0) :: (store 4 into stack, align 0) + ; X32: G_STORE [[ANYEXT]](s32), [[GEP]](p0) :: (store 4 into stack, align 1) ; X32: CALLpcrel32 @take_char, csr_32, implicit $esp, implicit $ssp ; X32: ADJCALLSTACKUP32 4, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: ADJCALLSTACKDOWN32 4, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp @@ -580,7 +580,7 @@ define void @test_abi_exts_call(i8* %addr) { ; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s32) ; X32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD1]](s8) - ; X32: G_STORE [[SEXT]](s32), [[GEP1]](p0) :: (store 4 into stack, align 0) + ; X32: G_STORE [[SEXT]](s32), [[GEP1]](p0) :: (store 4 into stack, align 1) ; X32: CALLpcrel32 @take_char, csr_32, implicit $esp, implicit $ssp ; X32: ADJCALLSTACKUP32 4, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: ADJCALLSTACKDOWN32 4, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp @@ -588,7 +588,7 @@ define void @test_abi_exts_call(i8* %addr) { ; X32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; X32: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[COPY2]], [[C2]](s32) ; X32: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s8) - ; X32: G_STORE [[ZEXT]](s32), [[GEP2]](p0) :: (store 4 into stack, align 0) + ; X32: G_STORE [[ZEXT]](s32), [[GEP2]](p0) :: (store 4 into stack, align 1) ; X32: CALLpcrel32 @take_char, csr_32, implicit $esp, implicit $ssp ; X32: ADJCALLSTACKUP32 4, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: RET 0 @@ -625,20 +625,20 @@ define void @test_variadic_call_1(i8** %addr_ptr, i32* %val_ptr) { ; X32-LABEL: name: test_variadic_call_1 ; X32: bb.1 (%ir-block.0): ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; X32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.1, align 0) + ; X32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.1, align 1) ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X32: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.0, align 1) ; X32: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.addr_ptr) ; X32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[LOAD1]](p0) :: (load 4 from %ir.val_ptr) ; X32: ADJCALLSTACKDOWN32 8, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: [[COPY:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s32) - ; X32: G_STORE [[LOAD2]](p0), [[GEP]](p0) :: (store 4 into stack, align 0) + ; X32: G_STORE [[LOAD2]](p0), [[GEP]](p0) :: (store 4 into stack, align 1) ; X32: [[COPY1:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s32) - ; X32: G_STORE [[LOAD3]](s32), [[GEP1]](p0) :: (store 4 into stack + 4, align 0) + ; X32: G_STORE [[LOAD3]](s32), [[GEP1]](p0) :: (store 4 into stack + 4, align 1) ; X32: CALLpcrel32 @variadic_callee, csr_32, implicit $esp, implicit $ssp ; X32: ADJCALLSTACKUP32 8, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: RET 0 @@ -666,20 +666,20 @@ define void @test_variadic_call_2(i8** %addr_ptr, double* %val_ptr) { ; X32-LABEL: name: test_variadic_call_2 ; X32: bb.1 (%ir-block.0): ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; X32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.1, align 0) + ; X32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.1, align 1) ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X32: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.0, align 1) ; X32: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.addr_ptr) ; X32: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[LOAD1]](p0) :: (load 8 from %ir.val_ptr, align 4) ; X32: ADJCALLSTACKDOWN32 12, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: [[COPY:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s32) - ; X32: G_STORE [[LOAD2]](p0), [[GEP]](p0) :: (store 4 into stack, align 0) + ; X32: G_STORE [[LOAD2]](p0), [[GEP]](p0) :: (store 4 into stack, align 1) ; X32: [[COPY1:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s32) - ; X32: G_STORE [[LOAD3]](s64), [[GEP1]](p0) :: (store 8 into stack + 4, align 0) + ; X32: G_STORE [[LOAD3]](s64), [[GEP1]](p0) :: (store 8 into stack + 4, align 1) ; X32: CALLpcrel32 @variadic_callee, csr_32, implicit $esp, implicit $ssp ; X32: ADJCALLSTACKUP32 12, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: RET 0 -- 2.7.4