From 2a5fb87de2e536cc82f184275edea755bec22f44 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 9 Jul 2020 11:49:32 +0200 Subject: [PATCH] radv: clean up binning state initialization It's no longer emitted directly in the pipeline. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_pipeline.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 62fd14d..1565f39 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3404,9 +3404,8 @@ radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipe } static void -radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs, - struct radv_pipeline *pipeline, - const VkGraphicsPipelineCreateInfo *pCreateInfo) +radv_pipeline_init_disabled_binning_state(struct radv_pipeline *pipeline, + const VkGraphicsPipelineCreateInfo *pCreateInfo) { uint32_t pa_sc_binner_cntl_0 = S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) | @@ -3476,10 +3475,9 @@ radv_get_binning_settings(const struct radv_physical_device *pdev) } static void -radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs, - struct radv_pipeline *pipeline, - const VkGraphicsPipelineCreateInfo *pCreateInfo, - const struct radv_blend_state *blend) +radv_pipeline_init_binning_state(struct radv_pipeline *pipeline, + const VkGraphicsPipelineCreateInfo *pCreateInfo, + const struct radv_blend_state *blend) { if (pipeline->device->physical_device->rad_info.chip_class < GFX9) return; @@ -3524,7 +3522,7 @@ radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs, pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0; pipeline->graphics.binning.db_dfsm_control = db_dfsm_control; } else - radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo); + radv_pipeline_init_disabled_binning_state(pipeline, pCreateInfo); } @@ -4666,7 +4664,6 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline, radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline); radv_pipeline_generate_ps_inputs(ctx_cs, pipeline); radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline); - radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend); radv_pipeline_generate_vgt_shader_config(ctx_cs, pipeline); radv_pipeline_generate_cliprect_rule(ctx_cs, pCreateInfo); radv_pipeline_generate_vgt_gs_out(ctx_cs, pipeline, pCreateInfo, extra); @@ -4898,6 +4895,8 @@ radv_pipeline_init(struct radv_pipeline *pipeline, radv_compute_vertex_input_state(pipeline, pCreateInfo); + radv_pipeline_init_binning_state(pipeline, pCreateInfo, &blend); + for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class); -- 2.7.4