From 2a2a0f38e7051fae47a0cae9e9cfd46180974949 Mon Sep 17 00:00:00 2001 From: Quentin Neill Date: Mon, 17 Jan 2011 18:40:36 +0000 Subject: [PATCH] Add support for TBM instructions. gas/ 2011-01-17 Quentin Neill * config/tc-i386.c (cpu_arch): Add CPU_TBM_FLAGS. * doc/c-i386.texi (i386-TBM): New section. opcodes/ 2011-01-17 Quentin Neill * i386-dis.c (REG_XOP_TBM_01): New. (REG_XOP_TBM_02): New. (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables. (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02 entries, and add bextr instruction. * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM. (cpu_flags): Add CpuTBM. * i386-opc.h (CpuTBM) New. (i386_cpu_flags): Add bit cputbm. * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk, blcs, blsfill, blsic, t1mskc, and tzmsk. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated gas/testsuite 2011-01-17 Quentin Neill * gas/i386/tbm.s: New. * gas/i386/tbm.d: New. * gas/i386/tbm-intel.d: New. * gas/i386/x86-64-tbm.s: New. * gas/i386/x86-64-tbm.d: New. * gas/i386/x86-64-tbm-intel.d: New. * gas/i386/arch-10.d: Add tbm flag and TBM instruction pattern. * gas/i386/arch-10.s: Add a TBM instruction. * gas/i386/arch-10-1.l: Add TBM instruction pattern. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. --- gas/ChangeLog | 6 ++++++ gas/config/tc-i386.c | 2 ++ gas/doc/c-i386.texi | 16 ++++++++++++++++ gas/testsuite/ChangeLog | 17 +++++++++++++++++ gas/testsuite/gas/i386/arch-10-1.l | 3 +++ gas/testsuite/gas/i386/arch-10-2.l | 3 +++ gas/testsuite/gas/i386/arch-10-3.l | 3 +++ gas/testsuite/gas/i386/arch-10-4.l | 3 +++ gas/testsuite/gas/i386/arch-10.d | 3 ++- gas/testsuite/gas/i386/arch-10.s | 2 ++ gas/testsuite/gas/i386/i386.exp | 4 ++++ gas/testsuite/gas/i386/x86-64-arch-2.d | 3 ++- gas/testsuite/gas/i386/x86-64-arch-2.s | 2 ++ opcodes/ChangeLog | 20 ++++++++++++++++++++ opcodes/i386-dis.c | 33 ++++++++++++++++++++++++++++----- opcodes/i386-gen.c | 3 +++ opcodes/i386-opc.h | 3 +++ opcodes/i386-opc.tbl | 12 ++++++++++++ 18 files changed, 131 insertions(+), 7 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index eb0c003..6d2768b 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2011-01-17 Quentin Neill + + * config/tc-i386.c (cpu_arch): Add CPU_TBM_FLAGS. + + * doc/c-i386.texi (i386-TBM): New section. + 2011-01-16 H.J. Lu * config/tc-i386.c (disallow_64bit_disp): Renamed to ... diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 74ceaca..ac15e81 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -733,6 +733,8 @@ static const arch_entry cpu_arch[] = CPU_ABM_FLAGS, 0, 0 }, { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, CPU_BMI_FLAGS, 0, 0 }, + { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, + CPU_TBM_FLAGS, 0, 0 }, }; #ifdef I386COFF diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index d330f86..be4de8a 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -36,6 +36,7 @@ extending the Intel architecture to 64-bits. * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations * i386-LWP:: AMD's Lightweight Profiling Instructions * i386-BMI:: Bit Manipulation Instruction +* i386-TBM:: AMD's Trailing Bit Manipulation Instructions * i386-16bit:: Writing 16-bit Code * i386-Arch:: Specifying an x86 CPU architecture * i386-Bugs:: AT&T Syntax bugs @@ -860,6 +861,21 @@ resetting. @c Need to add a specification citation here when available. +@node i386-TBM +@section AMD's Trailing Bit Manipulation Instructions + +@cindex TBM, i386 +@cindex TBM, x86-64 + +@code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM) +instruction set, available on AMD's BDVER2 processors (Trinity and +Viperfish). + +TBM instructions provide instructions implementing individual bit +manipulation operations such as isolating, masking, setting, resetting, +complementing, and operations on trailing zeros and ones. + +@c Need to add a specification citation here when available. @node i386-16bit @section Writing 16-bit Code diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 4be5d0d..c463b63 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,20 @@ +2011-01-17 Quentin Neill + + * gas/i386/tbm.s: New. + * gas/i386/tbm.d: New. + * gas/i386/tbm-intel.d: New. + * gas/i386/x86-64-tbm.s: New. + * gas/i386/x86-64-tbm.d: New. + * gas/i386/x86-64-tbm-intel.d: New. + * gas/i386/arch-10.d: Add tbm flag and TBM instruction pattern. + * gas/i386/arch-10.s: Add a TBM instruction. + * gas/i386/arch-10-1.l: Add TBM instruction pattern. + * gas/i386/arch-10-2.l: Likewise. + * gas/i386/arch-10-3.l: Likewise. + * gas/i386/arch-10-4.l: Likewise. + * gas/i386/x86-64-arch-2.s: Likewise. + * gas/i386/x86-64-arch-2.d: Likewise. + 2011-01-16 H.J. Lu * gas/i386/ilp32/immed64.s: New. diff --git a/gas/testsuite/gas/i386/arch-10-1.l b/gas/testsuite/gas/i386/arch-10-1.l index ee1e316..578252d 100644 --- a/gas/testsuite/gas/i386/arch-10-1.l +++ b/gas/testsuite/gas/i386/arch-10-1.l @@ -30,6 +30,7 @@ .*:60: Error: .* .*:62: Error: .* .*:64: Error: .* +.*:66: Error: .* GAS LISTING .* @@ -101,3 +102,5 @@ GAS LISTING .* [ ]*62[ ]+nopl \(%eax\) [ ]*63[ ]+\# BMI [ ]*64[ ]+blsr %ecx,%ebx +[ ]*65[ ]+\# TBM +[ ]*66[ ]+blcfill %ecx,%ebx diff --git a/gas/testsuite/gas/i386/arch-10-2.l b/gas/testsuite/gas/i386/arch-10-2.l index f1abcea..ae91ef1 100644 --- a/gas/testsuite/gas/i386/arch-10-2.l +++ b/gas/testsuite/gas/i386/arch-10-2.l @@ -29,6 +29,7 @@ .*:60: Error: .* .*:62: Error: .* .*:64: Error: .* +.*:66: Error: .* GAS LISTING .* @@ -100,3 +101,5 @@ GAS LISTING .* [ ]*62[ ]+nopl \(%eax\) [ ]*63[ ]+\# BMI [ ]*64[ ]+blsr %ecx,%ebx +[ ]*65[ ]+\# TBM +[ ]*66[ ]+blcfill %ecx,%ebx diff --git a/gas/testsuite/gas/i386/arch-10-3.l b/gas/testsuite/gas/i386/arch-10-3.l index 0b5d362..b15788e 100644 --- a/gas/testsuite/gas/i386/arch-10-3.l +++ b/gas/testsuite/gas/i386/arch-10-3.l @@ -22,6 +22,7 @@ .*:60: Error: .* .*:62: Error: .* .*:64: Error: .* +.*:66: Error: .* GAS LISTING .* @@ -96,3 +97,5 @@ GAS LISTING .* [ ]*62[ ]+nopl \(%eax\) [ ]*63[ ]+\# BMI [ ]*64[ ]+blsr %ecx,%ebx +[ ]*65[ ]+\# TBM +[ ]*66[ ]+blcfill %ecx,%ebx diff --git a/gas/testsuite/gas/i386/arch-10-4.l b/gas/testsuite/gas/i386/arch-10-4.l index 8cca603..f59185d 100644 --- a/gas/testsuite/gas/i386/arch-10-4.l +++ b/gas/testsuite/gas/i386/arch-10-4.l @@ -20,6 +20,7 @@ .*:60: Error: .* .*:62: Error: .* .*:64: Error: .* +.*:66: Error: .* GAS LISTING .* @@ -94,3 +95,5 @@ GAS LISTING .* [ ]*62[ ]+nopl \(%eax\) [ ]*63[ ]+\# BMI [ ]*64[ ]+blsr %ecx,%ebx +[ ]*65[ ]+\# TBM +[ ]*66[ ]+blcfill %ecx,%ebx diff --git a/gas/testsuite/gas/i386/arch-10.d b/gas/testsuite/gas/i386/arch-10.d index 2225fe0..65a58c5 100644 --- a/gas/testsuite/gas/i386/arch-10.d +++ b/gas/testsuite/gas/i386/arch-10.d @@ -1,4 +1,4 @@ -#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi +#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi+tbm #objdump: -dw #name: i386 arch 10 @@ -38,4 +38,5 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f a7 c0 xstore-rng [ ]*[a-f0-9]+: 0f 1f 00 nopl \(%eax\) [ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx +[ ]*[a-f0-9]+: 8f e9 60 01 c9 blcfill %ecx,%ebx #pass diff --git a/gas/testsuite/gas/i386/arch-10.s b/gas/testsuite/gas/i386/arch-10.s index f39f70b..0e72a76 100644 --- a/gas/testsuite/gas/i386/arch-10.s +++ b/gas/testsuite/gas/i386/arch-10.s @@ -62,3 +62,5 @@ xstorerng nopl (%eax) # BMI blsr %ecx,%ebx +# TBM +blcfill %ecx,%ebx diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 2d36fae..a0abf28 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -175,6 +175,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_dump_test "xop" run_dump_test "bmi" run_dump_test "bmi-intel" + run_dump_test "tbm" + run_dump_test "tbm-intel" run_dump_test "f16c" run_dump_test "f16c-intel" run_dump_test "fsgs" @@ -376,6 +378,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-xop" run_dump_test "x86-64-bmi" run_dump_test "x86-64-bmi-intel" + run_dump_test "x86-64-tbm" + run_dump_test "x86-64-tbm-intel" run_dump_test "x86-64-f16c" run_dump_test "x86-64-f16c-intel" run_dump_test "x86-64-fsgs" diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.d b/gas/testsuite/gas/i386/x86-64-arch-2.d index ac09453..824badd 100644 --- a/gas/testsuite/gas/i386/x86-64-arch-2.d +++ b/gas/testsuite/gas/i386/x86-64-arch-2.d @@ -1,4 +1,4 @@ -#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi +#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi+tbm #objdump: -dw #name: x86-64 arch 2 @@ -37,4 +37,5 @@ Disassembly of section .text: [ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx [ ]*[a-f0-9]+: 0f a7 c0 xstore-rng [ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx +[ ]*[a-f0-9]+: 8f e9 60 01 c9 blcfill %ecx,%ebx #pass diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.s b/gas/testsuite/gas/i386/x86-64-arch-2.s index 962f15e..5da17f6 100644 --- a/gas/testsuite/gas/i386/x86-64-arch-2.s +++ b/gas/testsuite/gas/i386/x86-64-arch-2.s @@ -60,3 +60,5 @@ lzcnt %ecx,%ebx xstorerng # BMI blsr %ecx,%ebx +# TBM +blcfill %ecx,%ebx diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8bc8139..cb391e9 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,23 @@ +2011-01-17 Quentin Neill + + * i386-dis.c (REG_XOP_TBM_01): New. + (REG_XOP_TBM_02): New. + (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables. + (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02 + entries, and add bextr instruction. + + * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM. + (cpu_flags): Add CpuTBM. + + * i386-opc.h (CpuTBM) New. + (i386_cpu_flags): Add bit cputbm. + + * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk, + blcs, blsfill, blsic, t1mskc, and tzmsk. + + * i386-init.h: Regenerated. + * i386-tbl.h: Regenerated + 2011-01-12 DJ Delorie * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg. diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 9e18bac..a4e16cb 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -601,7 +601,9 @@ enum REG_VEX_0FAE, REG_VEX_0F38F3, REG_XOP_LWPCB, - REG_XOP_LWP + REG_XOP_LWP, + REG_XOP_TBM_01, + REG_XOP_TBM_02 }; enum @@ -2779,6 +2781,27 @@ static const struct dis386 reg_table[][8] = { { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } }, { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } }, }, + /* REG_XOP_TBM_01 */ + { + { Bad_Opcode }, + { "blcfill", { { OP_LWP_E, 0 }, Ev } }, + { "blsfill", { { OP_LWP_E, 0 }, Ev } }, + { "blcs", { { OP_LWP_E, 0 }, Ev } }, + { "tzmsk", { { OP_LWP_E, 0 }, Ev } }, + { "blcic", { { OP_LWP_E, 0 }, Ev } }, + { "blsic", { { OP_LWP_E, 0 }, Ev } }, + { "t1mskc", { { OP_LWP_E, 0 }, Ev } }, + }, + /* REG_XOP_TBM_02 */ + { + { Bad_Opcode }, + { "blcmsk", { { OP_LWP_E, 0 }, Ev } }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "blci", { { OP_LWP_E, 0 }, Ev } }, + }, }; static const struct dis386 prefix_table[][4] = { @@ -6459,7 +6482,7 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 10 */ - { Bad_Opcode }, + { "bextr", { Gv, Ev, Iq } }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -6733,8 +6756,8 @@ static const struct dis386 xop_table[][256] = { { /* 00 */ { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { REG_TABLE (REG_XOP_TBM_01) }, + { REG_TABLE (REG_XOP_TBM_02) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7041,7 +7064,7 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 10 */ - { Bad_Opcode }, + { "bextr", { Gv, Ev, Iq } }, { Bad_Opcode }, { REG_TABLE (REG_XOP_LWP) }, { Bad_Opcode }, diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 4b2ed29..e791c61 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -142,6 +142,8 @@ static initializer cpu_flag_init[] = "CpuLWP" }, { "CPU_BMI_FLAGS", "CpuBMI" }, + { "CPU_TBM_FLAGS", + "CpuTBM" }, { "CPU_MOVBE_FLAGS", "CpuMovbe" }, { "CPU_RDTSCP_FLAGS", @@ -323,6 +325,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuXOP), BITFIELD (CpuLWP), BITFIELD (CpuBMI), + BITFIELD (CpuTBM), BITFIELD (CpuLM), BITFIELD (CpuMovbe), BITFIELD (CpuEPT), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 6696983..f90dff5 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -112,6 +112,8 @@ enum CpuLWP, /* BMI support required */ CpuBMI, + /* TBM support required */ + CpuTBM, /* MOVBE Instruction support required */ CpuMovbe, /* EPT Instructions required */ @@ -189,6 +191,7 @@ typedef union i386_cpu_flags unsigned int cpuxop:1; unsigned int cpulwp:1; unsigned int cpubmi:1; + unsigned int cputbm:1; unsigned int cpumovbe:1; unsigned int cpuept:1; unsigned int cpurdtscp:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 84fb818..bffe134 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -2742,6 +2742,18 @@ blsmsk, 2, 0xf3, 0x2, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=2| blsr, 2, 0xf3, 0x1, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 } tzcnt, 2, 0xf30fbc, None, 2, CpuBMI, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +// TBM instructions +bextr, 3, 0x10, None, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=5|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm32|Imm32S, Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +blcfill, 2, 0x01, 0x1, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +blci, 2, 0x02, 0x6, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +blcic, 2, 0x01, 0x5, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +blcmsk, 2, 0x02, 0x1, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +blcs, 2, 0x01, 0x3, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +blsfill, 2, 0x01, 0x2, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +blsic, 2, 0x01, 0x6, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +t1mskc, 2, 0x01, 0x7, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +tzmsk, 2, 0x01, 0x4, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } + // AMD 3DNow! instructions. prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } -- 2.7.4