From 29fe0e3490ef63f564f426fc526d4415f44e7052 Mon Sep 17 00:00:00 2001 From: ths Date: Tue, 25 Dec 2007 17:32:46 +0000 Subject: [PATCH] 5K and 20K are Release 1 CPUs. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3858 c046a42c-6fe2-441c-8c8c-71466251a162 --- target-mips/translate_init.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index b6077ba..a2dec0a 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -308,7 +308,7 @@ static mips_def_t mips_defs[] = { .name = "5Kc", .CP0_PRid = 0x00018100, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (MMU_TYPE_R4000 << CP0C0_MT), .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | @@ -327,7 +327,7 @@ static mips_def_t mips_defs[] = { .name = "5Kf", .CP0_PRid = 0x00018100, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (MMU_TYPE_R4000 << CP0C0_MT), .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | @@ -351,7 +351,7 @@ static mips_def_t mips_defs[] = /* We emulate a later version of the 20Kc, earlier ones had a broken WAIT instruction. */ .CP0_PRid = 0x000182a0, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI), .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | -- 2.7.4