From 2996a2b50fe39784b4c98748ba2a5b9595dc40f4 Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Tue, 5 Oct 2021 16:28:03 +0300 Subject: [PATCH] [X86][Costmodel] Load/store i32/f32 Stride=6 VF=8 interleaving costs The only sched models that for cpu's that support avx2 but not avx512 are: haswell, broadwell, skylake, zen1-3 For load we have: https://godbolt.org/z/jK85GWKaK - for intels `Block RThroughput: =31.0`; for ryzens, `Block RThroughput: <=17.0` So could pick cost of `31`. For store we have: https://godbolt.org/z/hPWWhEEf9 - for intels `Block RThroughput: =33.0`; for ryzens, `Block RThroughput: <=13.8` So we could pick cost of `33`. I'm directly using the shuffling asm the llc produced, without any manual fixups that may be needed to ensure sequential execution. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D111089 --- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 2 ++ llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll | 2 +- llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll | 2 +- llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll | 2 +- llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll | 2 +- 5 files changed, 6 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 3c11911..2099c92 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -5150,6 +5150,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( {6, MVT::v2i32, 6}, // (load 12i32 and) deinterleave into 6 x 2i32 {6, MVT::v4i32, 15}, // (load 24i32 and) deinterleave into 6 x 4i32 + {6, MVT::v8i32, 31}, // (load 48i32 and) deinterleave into 6 x 8i32 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32 }; @@ -5234,6 +5235,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( {6, MVT::v2i32, 9}, // interleave 6 x 2i32 into 12i32 (and store) {6, MVT::v4i32, 12}, // interleave 6 x 4i32 into 24i32 (and store) + {6, MVT::v8i32, 33}, // interleave 6 x 8i32 into 48i32 (and store) }; if (Opcode == Instruction::Load) { diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll index 021a9f0..674ba30 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll @@ -26,7 +26,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load float, float* %in0, align 4 ; AVX2: LV: Found an estimated cost of 8 for VF 2 For instruction: %v0 = load float, float* %in0, align 4 ; AVX2: LV: Found an estimated cost of 18 for VF 4 For instruction: %v0 = load float, float* %in0, align 4 -; AVX2: LV: Found an estimated cost of 114 for VF 8 For instruction: %v0 = load float, float* %in0, align 4 +; AVX2: LV: Found an estimated cost of 37 for VF 8 For instruction: %v0 = load float, float* %in0, align 4 ; AVX2: LV: Found an estimated cost of 228 for VF 16 For instruction: %v0 = load float, float* %in0, align 4 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load float, float* %in0, align 4 diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll index 89f54c37..ae69382 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll @@ -26,7 +26,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load i32, i32* %in0, align 4 ; AVX2: LV: Found an estimated cost of 8 for VF 2 For instruction: %v0 = load i32, i32* %in0, align 4 ; AVX2: LV: Found an estimated cost of 18 for VF 4 For instruction: %v0 = load i32, i32* %in0, align 4 -; AVX2: LV: Found an estimated cost of 138 for VF 8 For instruction: %v0 = load i32, i32* %in0, align 4 +; AVX2: LV: Found an estimated cost of 37 for VF 8 For instruction: %v0 = load i32, i32* %in0, align 4 ; AVX2: LV: Found an estimated cost of 276 for VF 16 For instruction: %v0 = load i32, i32* %in0, align 4 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load i32, i32* %in0, align 4 diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll b/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll index d9470e0..cd6912b 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll @@ -26,7 +26,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: store float %v5, float* %out5, align 4 ; AVX2: LV: Found an estimated cost of 11 for VF 2 For instruction: store float %v5, float* %out5, align 4 ; AVX2: LV: Found an estimated cost of 15 for VF 4 For instruction: store float %v5, float* %out5, align 4 -; AVX2: LV: Found an estimated cost of 114 for VF 8 For instruction: store float %v5, float* %out5, align 4 +; AVX2: LV: Found an estimated cost of 39 for VF 8 For instruction: store float %v5, float* %out5, align 4 ; AVX2: LV: Found an estimated cost of 228 for VF 16 For instruction: store float %v5, float* %out5, align 4 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: store float %v5, float* %out5, align 4 diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll b/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll index f35c795..1003d34 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll @@ -26,7 +26,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: store i32 %v5, i32* %out5, align 4 ; AVX2: LV: Found an estimated cost of 11 for VF 2 For instruction: store i32 %v5, i32* %out5, align 4 ; AVX2: LV: Found an estimated cost of 15 for VF 4 For instruction: store i32 %v5, i32* %out5, align 4 -; AVX2: LV: Found an estimated cost of 138 for VF 8 For instruction: store i32 %v5, i32* %out5, align 4 +; AVX2: LV: Found an estimated cost of 39 for VF 8 For instruction: store i32 %v5, i32* %out5, align 4 ; AVX2: LV: Found an estimated cost of 276 for VF 16 For instruction: store i32 %v5, i32* %out5, align 4 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: store i32 %v5, i32* %out5, align 4 -- 2.7.4