From 2988f940d861f0fa76bc5b749772f2b9239d5a1b Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 19 Jan 2021 14:28:30 +0000 Subject: [PATCH] [X86] Regenerate fmin/fmax reduction tests Add missing check-prefixes + v1f32 tests --- llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll | 33 +++++++++++++++--------- llvm/test/CodeGen/X86/vector-reduce-fmax.ll | 12 ++++----- llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll | 24 ++++++++--------- llvm/test/CodeGen/X86/vector-reduce-fmin.ll | 21 ++++++++++----- 4 files changed, 54 insertions(+), 36 deletions(-) diff --git a/llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll b/llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll index 021c48d..1672481 100644 --- a/llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll +++ b/llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll @@ -1,15 +1,23 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefix=AVX512 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefix=AVX512 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=ALL,SSE,SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=ALL,SSE,SSE41 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=ALL,AVX +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=ALL,AVX +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=ALL,AVX512 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=ALL,AVX512 ; ; vXf32 ; +define float @test_v1f32(<1 x float> %a0) { +; ALL-LABEL: test_v1f32: +; ALL: # %bb.0: +; ALL-NEXT: retq + %1 = call nnan float @llvm.vector.reduce.fmax.v1f32(<1 x float> %a0) + ret float %1 +} + define float @test_v2f32(<2 x float> %a0) { ; SSE2-LABEL: test_v2f32: ; SSE2: # %bb.0: @@ -458,10 +466,10 @@ define half @test_v2f16(<2 x half> %a0) nounwind { ; SSE-NEXT: subq $16, %rsp ; SSE-NEXT: movl %edi, %ebx ; SSE-NEXT: movzwl %si, %edi -; SSE-NEXT: callq __gnu_h2f_ieee +; SSE-NEXT: callq __gnu_h2f_ieee@PLT ; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; SSE-NEXT: movzwl %bx, %edi -; SSE-NEXT: callq __gnu_h2f_ieee +; SSE-NEXT: callq __gnu_h2f_ieee@PLT ; SSE-NEXT: movaps %xmm0, %xmm1 ; SSE-NEXT: cmpunordss %xmm0, %xmm1 ; SSE-NEXT: movaps %xmm1, %xmm2 @@ -471,7 +479,7 @@ define half @test_v2f16(<2 x half> %a0) nounwind { ; SSE-NEXT: andnps %xmm3, %xmm1 ; SSE-NEXT: orps %xmm2, %xmm1 ; SSE-NEXT: movaps %xmm1, %xmm0 -; SSE-NEXT: callq __gnu_f2h_ieee +; SSE-NEXT: callq __gnu_f2h_ieee@PLT ; SSE-NEXT: addq $16, %rsp ; SSE-NEXT: popq %rbx ; SSE-NEXT: retq @@ -482,16 +490,16 @@ define half @test_v2f16(<2 x half> %a0) nounwind { ; AVX-NEXT: subq $16, %rsp ; AVX-NEXT: movl %esi, %ebx ; AVX-NEXT: movzwl %di, %edi -; AVX-NEXT: callq __gnu_h2f_ieee +; AVX-NEXT: callq __gnu_h2f_ieee@PLT ; AVX-NEXT: vmovss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; AVX-NEXT: movzwl %bx, %edi -; AVX-NEXT: callq __gnu_h2f_ieee +; AVX-NEXT: callq __gnu_h2f_ieee@PLT ; AVX-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 4-byte Reload ; AVX-NEXT: # xmm2 = mem[0],zero,zero,zero ; AVX-NEXT: vmaxss %xmm2, %xmm0, %xmm1 ; AVX-NEXT: vcmpunordss %xmm2, %xmm2, %xmm2 ; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 -; AVX-NEXT: callq __gnu_f2h_ieee +; AVX-NEXT: callq __gnu_f2h_ieee@PLT ; AVX-NEXT: addq $16, %rsp ; AVX-NEXT: popq %rbx ; AVX-NEXT: retq @@ -514,6 +522,7 @@ define half @test_v2f16(<2 x half> %a0) nounwind { %1 = call nnan half @llvm.vector.reduce.fmax.v2f16(<2 x half> %a0) ret half %1 } +declare float @llvm.vector.reduce.fmax.v1f32(<1 x float>) declare float @llvm.vector.reduce.fmax.v2f32(<2 x float>) declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>) declare float @llvm.vector.reduce.fmax.v8f32(<8 x float>) diff --git a/llvm/test/CodeGen/X86/vector-reduce-fmax.ll b/llvm/test/CodeGen/X86/vector-reduce-fmax.ll index af8141a..d7d754a 100644 --- a/llvm/test/CodeGen/X86/vector-reduce-fmax.ll +++ b/llvm/test/CodeGen/X86/vector-reduce-fmax.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX512,AVX512BW -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=AVX512,AVX512VL +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=ALL,SSE,SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=ALL,SSE,SSE41 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=ALL,AVX +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=ALL,AVX +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=ALL,AVX512,AVX512BW +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=ALL,AVX512,AVX512VL ; ; vXf32 diff --git a/llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll b/llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll index 0ec707b..9991290 100644 --- a/llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll +++ b/llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefix=AVX512 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefix=AVX512 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=ALL,SSE,SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=ALL,SSE,SSE41 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=ALL,AVX +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=ALL,AVX +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=ALL,AVX512 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=ALL,AVX512 ; ; vXf32 @@ -465,10 +465,10 @@ define half @test_v2f16(<2 x half> %a0) nounwind { ; SSE-NEXT: subq $16, %rsp ; SSE-NEXT: movl %edi, %ebx ; SSE-NEXT: movzwl %si, %edi -; SSE-NEXT: callq __gnu_h2f_ieee +; SSE-NEXT: callq __gnu_h2f_ieee@PLT ; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; SSE-NEXT: movzwl %bx, %edi -; SSE-NEXT: callq __gnu_h2f_ieee +; SSE-NEXT: callq __gnu_h2f_ieee@PLT ; SSE-NEXT: movaps %xmm0, %xmm1 ; SSE-NEXT: cmpunordss %xmm0, %xmm1 ; SSE-NEXT: movaps %xmm1, %xmm2 @@ -478,7 +478,7 @@ define half @test_v2f16(<2 x half> %a0) nounwind { ; SSE-NEXT: andnps %xmm3, %xmm1 ; SSE-NEXT: orps %xmm2, %xmm1 ; SSE-NEXT: movaps %xmm1, %xmm0 -; SSE-NEXT: callq __gnu_f2h_ieee +; SSE-NEXT: callq __gnu_f2h_ieee@PLT ; SSE-NEXT: addq $16, %rsp ; SSE-NEXT: popq %rbx ; SSE-NEXT: retq @@ -489,16 +489,16 @@ define half @test_v2f16(<2 x half> %a0) nounwind { ; AVX-NEXT: subq $16, %rsp ; AVX-NEXT: movl %esi, %ebx ; AVX-NEXT: movzwl %di, %edi -; AVX-NEXT: callq __gnu_h2f_ieee +; AVX-NEXT: callq __gnu_h2f_ieee@PLT ; AVX-NEXT: vmovss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; AVX-NEXT: movzwl %bx, %edi -; AVX-NEXT: callq __gnu_h2f_ieee +; AVX-NEXT: callq __gnu_h2f_ieee@PLT ; AVX-NEXT: vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 4-byte Reload ; AVX-NEXT: # xmm2 = mem[0],zero,zero,zero ; AVX-NEXT: vminss %xmm2, %xmm0, %xmm1 ; AVX-NEXT: vcmpunordss %xmm2, %xmm2, %xmm2 ; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 -; AVX-NEXT: callq __gnu_f2h_ieee +; AVX-NEXT: callq __gnu_f2h_ieee@PLT ; AVX-NEXT: addq $16, %rsp ; AVX-NEXT: popq %rbx ; AVX-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vector-reduce-fmin.ll b/llvm/test/CodeGen/X86/vector-reduce-fmin.ll index 29a37f2..8201072 100644 --- a/llvm/test/CodeGen/X86/vector-reduce-fmin.ll +++ b/llvm/test/CodeGen/X86/vector-reduce-fmin.ll @@ -1,15 +1,23 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX512,AVX512BW -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=AVX512,AVX512VL +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=ALL,SSE,SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=ALL,SSE,SSE41 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=ALL,AVX +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=ALL,AVX +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=ALL,AVX512,AVX512BW +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=ALL,AVX512,AVX512VL ; ; vXf32 ; +define float @test_v1f32(<1 x float> %a0) { +; ALL-LABEL: test_v1f32: +; ALL: # %bb.0: +; ALL-NEXT: retq + %1 = call float @llvm.vector.reduce.fmin.v1f32(<1 x float> %a0) + ret float %1 +} + define float @test_v2f32(<2 x float> %a0) { ; SSE2-LABEL: test_v2f32: ; SSE2: # %bb.0: @@ -1086,6 +1094,7 @@ define double @test_v16f64(<16 x double> %a0) { ret double %1 } +declare float @llvm.vector.reduce.fmin.v1f32(<1 x float>) declare float @llvm.vector.reduce.fmin.v2f32(<2 x float>) declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>) declare float @llvm.vector.reduce.fmin.v8f32(<8 x float>) -- 2.7.4