From 2984b3f8c24b87ba4d57e213d593b2f91a4a31dd Mon Sep 17 00:00:00 2001 From: Lichao Liu Date: Thu, 11 Jun 2020 17:59:24 +0800 Subject: [PATCH] MIPS: Loongson-2EF: disable fix-loongson3-llsc in compiler Firstly, Loongson-2EF support ll/sc instructions, but doesn't need fix-loongson3-llsc compile option. Secondly, fix-loongson3-llsc will cause kernel startup fail at futex_init, because compiler will add 'sync' before 'll', which will affect __ex_table. futex_init will pass NULL uaddr parameter to futex_atomic_cmpxchg_inatomic. futex_atomic_cmpxchg_inatomic will access uaddr directly, which will cause page fault exception, the exception should be handled by __ex_table's nextinsn if the exception insn exsit in __ex_table. Because __ex_table is affected by compiler, the exception can not be handled, and futex_atomic_cmpxchg_inatomic will crash. Error code as below: __ex_table.insn = 1b, which is 'sync' compiled with fix-loongson3-llsc, but the actual exception instrction is ll. So, do_page_fault will not find the correct inst in __ex_table, and can not handle this exception. "1: "user_ll("%1", "%3")" \n" " bne %1, %z4, 3f \n" " .set pop \n" " move $1, %z5 \n" " .set "MIPS_ISA_ARCH_LEVEL" \n" "2: "user_sc("$1", "%2")" \n" " beqz $1, 1b \n" "3: " __SYNC_ELSE(full, loongson3_war, __WEAK_LLSC_MB) "\n" " .insn \n" " .set pop \n" " .section .fixup,\"ax\" \n" "4: li %0, %6 \n" " j 3b \n" " .previous \n" " .section __ex_table,\"a\" \n" " "__UA_ADDR "\t1b, 4b \n" " "__UA_ADDR "\t2b, 4b \n" " .previous Signed-off-by: Lichao Liu Reviewed-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/loongson2ef/Platform | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/mips/loongson2ef/Platform b/arch/mips/loongson2ef/Platform index cdad3c1..4ab55f1 100644 --- a/arch/mips/loongson2ef/Platform +++ b/arch/mips/loongson2ef/Platform @@ -8,6 +8,28 @@ cflags-$(CONFIG_CPU_LOONGSON2E) += \ $(call cc-option,-march=loongson2e,-march=r4600) cflags-$(CONFIG_CPU_LOONGSON2F) += \ $(call cc-option,-march=loongson2f,-march=r4600) +# +# Some versions of binutils, not currently mainline as of 2019/02/04, support +# an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction +# to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h for a +# description). +# +# We disable this in order to prevent the assembler meddling with the +# instruction that labels refer to, ie. if we label an ll instruction: +# +# 1: ll v0, 0(a0) +# +# ...then with the assembler fix applied the label may actually point at a sync +# instruction inserted by the assembler, and if we were using the label in an +# exception table the table would no longer contain the address of the ll +# instruction. +# +# Avoid this by explicitly disabling that assembler behaviour. If upstream +# binutils does not merge support for the flag then we can revisit & remove +# this later - for now it ensures vendor toolchains don't cause problems. +# +cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,) + # Enable the workarounds for Loongson2f ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),) -- 2.7.4