From 29621b2534658426128ec30455db98c105964c51 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sun, 9 Feb 2020 14:23:19 +0000 Subject: [PATCH] [X86] Rename matchShuffleAsRotate - matchShuffleAsByteRotate. NFCI. A matchShuffleAsBitRotate variant will be added soon and we need to make the difference more obvious. --- llvm/lib/Target/X86/X86ISelLowering.cpp | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 408e423..3f20274 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -11665,10 +11665,11 @@ static SDValue lowerShuffleAsDecomposedShuffleBlend( return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask); } -/// Try to lower a vector shuffle as a rotation. +/// Try to lower a vector shuffle as a byte rotation. /// /// This is used for support PALIGNR for SSSE3 or VALIGND/Q for AVX512. -static int matchShuffleAsRotate(SDValue &V1, SDValue &V2, ArrayRef Mask) { +static int matchShuffleAsByteRotate(SDValue &V1, SDValue &V2, + ArrayRef Mask) { int NumElts = Mask.size(); // We need to detect various ways of spelling a rotation: @@ -11763,7 +11764,7 @@ static int matchShuffleAsByteRotate(MVT VT, SDValue &V1, SDValue &V2, if (!is128BitLaneRepeatedShuffleMask(VT, Mask, RepeatedMask)) return -1; - int Rotation = matchShuffleAsRotate(V1, V2, RepeatedMask); + int Rotation = matchShuffleAsByteRotate(V1, V2, RepeatedMask); if (Rotation <= 0) return -1; @@ -11843,7 +11844,7 @@ static SDValue lowerShuffleAsVALIGN(const SDLoc &DL, MVT VT, SDValue V1, && "VLX required for 128/256-bit vectors"); SDValue Lo = V1, Hi = V2; - int Rotation = matchShuffleAsRotate(Lo, Hi, Mask); + int Rotation = matchShuffleAsByteRotate(Lo, Hi, Mask); if (Rotation <= 0) return SDValue(); -- 2.7.4