From 29159de4f19e02dae057f3478ca83dc7b9d1717d Mon Sep 17 00:00:00 2001 From: Jian Hu Date: Sun, 28 Apr 2019 12:27:39 +0800 Subject: [PATCH] clk: tm2: fix pcie A and B clock [1/1] PD#SWPL-7855 Problem: pcie A does not equal 100M when enable alone, enable pcie A and B together works well. Solution: correct pcie A and B clock describetion Verify: test passed on tm2 ab3100 Change-Id: I9483efe00cc157c3ff5a9ff4d3a03e0dc50e4fdc Signed-off-by: Jian Hu --- drivers/amlogic/clk/tm2/tm2.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/amlogic/clk/tm2/tm2.c b/drivers/amlogic/clk/tm2/tm2.c index 529d42d..2ff1dc2 100644 --- a/drivers/amlogic/clk/tm2/tm2.c +++ b/drivers/amlogic/clk/tm2/tm2.c @@ -79,8 +79,8 @@ static struct clk_gate tm2_pcie01_enable = { }; static struct clk_gate tm2_pcie0_gate = { - .reg = (void *)HHI_PCIE_PLL_CNTL1, - .bit_idx = 28, + .reg = (void *)HHI_PCIE_PLL_CNTL5, + .bit_idx = 3, .lock = &clk_lock, .hw.init = &(struct clk_init_data){ .name = "tm2_pcie0_gate", @@ -92,8 +92,8 @@ static struct clk_gate tm2_pcie0_gate = { }; static struct clk_gate tm2_pcie1_gate = { - .reg = (void *)HHI_PCIE_PLL_CNTL5, - .bit_idx = 3, + .reg = (void *)HHI_PCIE_PLL_CNTL1, + .bit_idx = 28, .lock = &clk_lock, .hw.init = &(struct clk_init_data){ .name = "tm2_pcie1_gate", -- 2.7.4