From 28da9558f50a4b015799cf128c5914c9c5e93862 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Samuel=20Iglesias=20Gons=C3=A1lvez?= Date: Fri, 13 Sep 2019 01:34:35 +0300 Subject: [PATCH] i965/fs/generator: refactor rounding mode helper in preparation for float controls MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit v2: - Fix bug in defining BRW_CR0_FP_MODE_MASK. v3: - Update comment (Caio). v4: - Split the patch into the helper (this one) and the new opcode (Caio). Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Caio Marcelo de Oliveira Filho --- src/intel/compiler/brw_eu.h | 4 +-- src/intel/compiler/brw_eu_emit.c | 52 +++++++++++++-------------------- src/intel/compiler/brw_fs_generator.cpp | 11 +++++-- 3 files changed, 32 insertions(+), 35 deletions(-) diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h index cb23c9f..306c24a 100644 --- a/src/intel/compiler/brw_eu.h +++ b/src/intel/compiler/brw_eu.h @@ -1145,8 +1145,8 @@ brw_broadcast(struct brw_codegen *p, struct brw_reg idx); void -brw_rounding_mode(struct brw_codegen *p, - enum brw_rnd_mode mode); +brw_float_controls_mode(struct brw_codegen *p, + unsigned mode, unsigned mask); /*********************************************************************** * brw_eu_util.c: diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index c26a22f..2825402 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -3476,37 +3476,27 @@ brw_WAIT(struct brw_codegen *p) brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE); } -/** - * Changes the floating point rounding mode updating the control register - * field defined at cr0.0[5-6] bits. This function supports the changes to - * RTNE (00), RU (01), RD (10) and RTZ (11) rounding using bitwise operations. - * Only RTNE and RTZ rounding are enabled at nir. - */ void -brw_rounding_mode(struct brw_codegen *p, - enum brw_rnd_mode mode) -{ - const unsigned bits = mode << BRW_CR0_RND_MODE_SHIFT; - - if (bits != BRW_CR0_RND_MODE_MASK) { - brw_inst *inst = brw_AND(p, brw_cr0_reg(0), brw_cr0_reg(0), - brw_imm_ud(~BRW_CR0_RND_MODE_MASK)); - brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1); - - /* From the Skylake PRM, Volume 7, page 760: - * "Implementation Restriction on Register Access: When the control - * register is used as an explicit source and/or destination, hardware - * does not ensure execution pipeline coherency. Software must set the - * thread control field to ‘switch’ for an instruction that uses - * control register as an explicit operand." - */ - brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH); - } - - if (bits) { - brw_inst *inst = brw_OR(p, brw_cr0_reg(0), brw_cr0_reg(0), - brw_imm_ud(bits)); - brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1); - brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH); +brw_float_controls_mode(struct brw_codegen *p, + unsigned mode, unsigned mask) +{ + brw_inst *inst = brw_AND(p, brw_cr0_reg(0), brw_cr0_reg(0), + brw_imm_ud(~mask)); + brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1); + + /* From the Skylake PRM, Volume 7, page 760: + * "Implementation Restriction on Register Access: When the control + * register is used as an explicit source and/or destination, hardware + * does not ensure execution pipeline coherency. Software must set the + * thread control field to ‘switch’ for an instruction that uses + * control register as an explicit operand." + */ + brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH); + + if (mode) { + brw_inst *inst_or = brw_OR(p, brw_cr0_reg(0), brw_cr0_reg(0), + brw_imm_ud(mode)); + brw_inst_set_exec_size(p->devinfo, inst_or, BRW_EXECUTE_1); + brw_inst_set_thread_control(p->devinfo, inst_or, BRW_THREAD_SWITCH); } } diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index b6e6925..48ac635 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -2218,9 +2218,16 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F)); break; - case SHADER_OPCODE_RND_MODE: + case SHADER_OPCODE_RND_MODE: { assert(src[0].file == BRW_IMMEDIATE_VALUE); - brw_rounding_mode(p, (brw_rnd_mode) src[0].d); + /* + * Changes the floating point rounding mode updating the control + * register field defined at cr0.0[5-6] bits. + */ + enum brw_rnd_mode mode = + (enum brw_rnd_mode) (src[0].d << BRW_CR0_RND_MODE_SHIFT); + brw_float_controls_mode(p, mode, BRW_CR0_RND_MODE_MASK); + } break; default: -- 2.7.4