From 28a2ab9fe9ba6387999d701d640ef4c787b9e574 Mon Sep 17 00:00:00 2001 From: uros Date: Sat, 15 Mar 2008 11:17:05 +0000 Subject: [PATCH] * config/i386/mmx.md ("sse2_umulv1siv2di3"): Rename from "sse2_umulsidi3". Use V1DI mode for operand 0. ("mmx_psadbw"): Use V1DI mode for operand 0. * config/i386/i386-modes.def (V1SI): New vector mode. * config/i386/i386.c (struct builtin_description) [IX86_BUILTIN_PMULUDQ]: Use CODE_FOR_sse2_umulv1siv1di3. (v1di_ftype_v8qi_v8qi): Rename from di_ftype_v8qi_v8qi. (v1di_ftype_v2si_v2si): Rename from di_ftype_v2si_v2si. (ix86_init_mmx_sse_builtins) [__builtin_ia32_psadbw]: Use v1di_ftype_v8qi_v8qi type. [__builtin_ia32_pmuludq]: Use v1di_ftype_v2si_v2si type. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@133243 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 17 +++++++++++++++++ gcc/config/i386/i386-modes.def | 1 + gcc/config/i386/i386.c | 14 +++++++------- gcc/config/i386/mmx.md | 22 +++++++++++----------- gcc/doc/extend.texi | 4 ++-- 5 files changed, 38 insertions(+), 20 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e640f6c..36867fc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,20 @@ +2008-03-15 Uros Bizjak + + * config/i386/mmx.md ("sse2_umulv1siv2di3"): Rename from + "sse2_umulsidi3". Use V1DI mode for operand 0. + ("mmx_psadbw"): Use V1DI mode for operand 0. + * config/i386/i386-modes.def (V1SI): New vector mode. + * config/i386/i386.c (struct builtin_description) + [IX86_BUILTIN_PMULUDQ]: Use CODE_FOR_sse2_umulv1siv1di3. + (v1di_ftype_v8qi_v8qi): Rename from di_ftype_v8qi_v8qi. + (v1di_ftype_v2si_v2si): Rename from di_ftype_v2si_v2si. + (ix86_init_mmx_sse_builtins) [__builtin_ia32_psadbw]: Use + v1di_ftype_v8qi_v8qi type. + [__builtin_ia32_pmuludq]: Use v1di_ftype_v2si_v2si type. + + * doc/extend.texi (X86 Built-in Functions) [__builtin_ia32_psadbw, + __builtin_ia32_pmuludq]: Fix the mode of return value. + 2008-03-15 Richard Guenther PR middle-end/35595 diff --git a/gcc/config/i386/i386-modes.def b/gcc/config/i386/i386-modes.def index a23e820..d94b1b9 100644 --- a/gcc/config/i386/i386-modes.def +++ b/gcc/config/i386/i386-modes.def @@ -80,6 +80,7 @@ VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */ VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */ VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */ VECTOR_MODE (INT, DI, 1); /* V1DI */ +VECTOR_MODE (INT, SI, 1); /* V1SI */ VECTOR_MODE (INT, QI, 2); /* V2QI */ VECTOR_MODE (INT, DI, 4); /* V4DI */ VECTOR_MODE (INT, SI, 8); /* V8SI */ diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 74b2be2..883f226 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -18122,7 +18122,7 @@ static const struct builtin_description bdesc_2arg[] = { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, 0 }, { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, 0, IX86_BUILTIN_PSADBW128, UNKNOWN, 0 }, - { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulsidi3, 0, IX86_BUILTIN_PMULUDQ, UNKNOWN, 0 }, + { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, 0, IX86_BUILTIN_PMULUDQ, UNKNOWN, 0 }, { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, 0, IX86_BUILTIN_PMULUDQ128, UNKNOWN, 0 }, { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, 0, IX86_BUILTIN_PMADDWD128, UNKNOWN, 0 }, @@ -18826,11 +18826,11 @@ ix86_init_mmx_sse_builtins (void) tree v4si_ftype_v8hi_v8hi = build_function_type_list (V4SI_type_node, V8HI_type_node, V8HI_type_node, NULL_TREE); - tree di_ftype_v8qi_v8qi - = build_function_type_list (long_long_unsigned_type_node, + tree v1di_ftype_v8qi_v8qi + = build_function_type_list (V1DI_type_node, V8QI_type_node, V8QI_type_node, NULL_TREE); - tree di_ftype_v2si_v2si - = build_function_type_list (long_long_unsigned_type_node, + tree v1di_ftype_v2si_v2si + = build_function_type_list (V1DI_type_node, V2SI_type_node, V2SI_type_node, NULL_TREE); tree v2di_ftype_v16qi_v16qi = build_function_type_list (V2DI_type_node, @@ -19318,7 +19318,7 @@ ix86_init_mmx_sse_builtins (void) def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_sfence", void_ftype_void, IX86_BUILTIN_SFENCE); - def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_psadbw", di_ftype_v8qi_v8qi, IX86_BUILTIN_PSADBW); + def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_psadbw", v1di_ftype_v8qi_v8qi, IX86_BUILTIN_PSADBW); def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rcpps", v4sf_ftype_v4sf, IX86_BUILTIN_RCPPS); def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rcpss", v4sf_ftype_v4sf, IX86_BUILTIN_RCPSS); @@ -19422,7 +19422,7 @@ ix86_init_mmx_sse_builtins (void) def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LOADDQU); def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU); - def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmuludq", di_ftype_v2si_v2si, IX86_BUILTIN_PMULUDQ); + def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmuludq", v1di_ftype_v2si_v2si, IX86_BUILTIN_PMULUDQ); def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128); def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLDQI128); diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 1d2a41d..2238a3f 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -699,15 +699,15 @@ [(set_attr "type" "mmxmul") (set_attr "mode" "DI")]) -(define_insn "sse2_umulsidi3" - [(set (match_operand:DI 0 "register_operand" "=y") - (mult:DI - (zero_extend:DI - (vec_select:SI +(define_insn "sse2_umulv1siv1di3" + [(set (match_operand:V1DI 0 "register_operand" "=y") + (mult:V1DI + (zero_extend:V1DI + (vec_select:V1SI (match_operand:V2SI 1 "nonimmediate_operand" "%0") (parallel [(const_int 0)]))) - (zero_extend:DI - (vec_select:SI + (zero_extend:V1DI + (vec_select:V1SI (match_operand:V2SI 2 "nonimmediate_operand" "ym") (parallel [(const_int 0)])))))] "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V2SImode, operands)" @@ -1293,10 +1293,10 @@ (set_attr "mode" "DI")]) (define_insn "mmx_psadbw" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(match_operand:V8QI 1 "register_operand" "0") - (match_operand:V8QI 2 "nonimmediate_operand" "ym")] - UNSPEC_PSADBW))] + [(set (match_operand:V1DI 0 "register_operand" "=y") + (unspec:V1DI [(match_operand:V8QI 1 "register_operand" "0") + (match_operand:V8QI 2 "nonimmediate_operand" "ym")] + UNSPEC_PSADBW))] "TARGET_SSE || TARGET_3DNOW_A" "psadbw\t{%2, %0|%0, %2}" [(set_attr "type" "mmxshft") diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 53ec6ef..26a8e70 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -7505,7 +7505,7 @@ instruction that is part of the name. v4hi __builtin_ia32_pmulhuw (v4hi, v4hi) v8qi __builtin_ia32_pavgb (v8qi, v8qi) v4hi __builtin_ia32_pavgw (v4hi, v4hi) -v4hi __builtin_ia32_psadbw (v8qi, v8qi) +v1di __builtin_ia32_psadbw (v8qi, v8qi) v8qi __builtin_ia32_pmaxub (v8qi, v8qi) v4hi __builtin_ia32_pmaxsw (v4hi, v4hi) v8qi __builtin_ia32_pminub (v8qi, v8qi) @@ -7753,7 +7753,7 @@ void __builtin_ia32_lfence (void) void __builtin_ia32_mfence (void) v16qi __builtin_ia32_loaddqu (const char *) void __builtin_ia32_storedqu (char *, v16qi) -unsigned long long __builtin_ia32_pmuludq (v2si, v2si) +v1di __builtin_ia32_pmuludq (v2si, v2si) v2di __builtin_ia32_pmuludq128 (v4si, v4si) v8hi __builtin_ia32_psllw128 (v8hi, v8hi) v4si __builtin_ia32_pslld128 (v4si, v4si) -- 2.7.4