From 288c73e7be40be735b98a548983b4b58aa770e27 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sun, 29 Apr 2018 18:18:51 +0000 Subject: [PATCH] [X86] Remove unnecessary BT InstRW overrides. llvm-svn: 331147 --- llvm/lib/Target/X86/X86ScheduleZnver1.td | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index cea4c68..76b7f10 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -554,10 +554,7 @@ def ZnWriteALULat2Ld : SchedWriteRes<[ZnAGU, ZnALU]> { } // BT. -// r,r/i. -def : InstRW<[WriteShift], (instregex "BT(16|32|64)r(r|i8)")>; - -def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mr")>; +// m,i. def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>; // BTR BTS BTC. @@ -568,7 +565,6 @@ def ZnWriteBTRSC : SchedWriteRes<[ZnALU]> { } def : InstRW<[ZnWriteBTRSC], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>; - // m,r,i. def ZnWriteBTRSCm : SchedWriteRes<[ZnAGU, ZnALU]> { let Latency = 6; -- 2.7.4