From 2858038696b9672ef50cd38904fec510bc814584 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 21 Jun 2016 17:30:35 +0200 Subject: [PATCH] clk: tegra: Mark timer clock as critical The timer clock feeds the timer block, which, among other things, is used to drive the SOR lane sequencer. Since the Tegra timer driver is not enabled on 64-bit ARM, nothing currently claims that clock and it gets disabled by the common clock framework at late_init time. Given the non-obvious dependencies, the timer clock can be considered a critical part of the SoC infrastructure, requiring its clock source to be always on. Acked-by: Rhyland Klein Acked-by: Peter De Schrijver Signed-off-by: Thierry Reding --- drivers/clk/tegra/clk-tegra-periph.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index af85c8a..4ce4e7fb 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -792,7 +792,7 @@ static struct tegra_periph_init_data periph_clks[] = { static struct tegra_periph_init_data gate_clks[] = { GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0), - GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0), + GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL), GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0), GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0), GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0), -- 2.7.4