From 281a19cf7b9951e12ac25436728f8a978d3966d6 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 22 Mar 2018 06:15:08 +0000 Subject: [PATCH] [TableGen] Add a non-default constructor to CodeGenSchedClass and use it via emplace_back to create new SchedClasses instead of using resize(size+1) llvm-svn: 328183 --- llvm/utils/TableGen/CodeGenSchedule.cpp | 23 +++++++++-------------- llvm/utils/TableGen/CodeGenSchedule.h | 7 ++++--- 2 files changed, 13 insertions(+), 17 deletions(-) diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp index a21e44b..1f812fd 100644 --- a/llvm/utils/TableGen/CodeGenSchedule.cpp +++ b/llvm/utils/TableGen/CodeGenSchedule.cpp @@ -557,10 +557,9 @@ unsigned CodeGenSchedModels::findOrInsertRW(ArrayRef Seq, void CodeGenSchedModels::collectSchedClasses() { // NoItinerary is always the first class at Idx=0 - SchedClasses.resize(1); - SchedClasses.back().Index = 0; - SchedClasses.back().Name = "NoInstrModel"; - SchedClasses.back().ItinClassDef = Records.getDef("NoItinerary"); + assert(SchedClasses.empty() && "Expected empty sched class"); + SchedClasses.emplace_back(0, "NoInstrModel", + Records.getDef("NoItinerary")); SchedClasses.back().ProcIndices.push_back(0); // Create a SchedClass for each unique combination of itinerary class and @@ -572,9 +571,7 @@ void CodeGenSchedModels::collectSchedClasses() { findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads); // ProcIdx == 0 indicates the class applies to all processors. - IdxVec ProcIndices(1, 0); - - unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices); + unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, /*ProcIndices*/{0}); InstrClassMap[Inst->TheDef] = SCIdx; } // Create classes for InstRW defs. @@ -716,11 +713,11 @@ unsigned CodeGenSchedModels::addSchedClass(Record *ItinClassDef, return Idx; } Idx = SchedClasses.size(); - SchedClasses.resize(Idx+1); + SchedClasses.emplace_back(Idx, + createSchedClassName(ItinClassDef, OperWrites, + OperReads), + ItinClassDef); CodeGenSchedClass &SC = SchedClasses.back(); - SC.Index = Idx; - SC.Name = createSchedClassName(ItinClassDef, OperWrites, OperReads); - SC.ItinClassDef = ItinClassDef; SC.Writes = OperWrites; SC.Reads = OperReads; SC.ProcIndices = ProcIndices; @@ -788,10 +785,8 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) { } } unsigned SCIdx = SchedClasses.size(); - SchedClasses.resize(SCIdx+1); + SchedClasses.emplace_back(SCIdx, createSchedClassName(InstDefs), nullptr); CodeGenSchedClass &SC = SchedClasses.back(); - SC.Index = SCIdx; - SC.Name = createSchedClassName(InstDefs); DEBUG(dbgs() << "InstRW: New SC " << SCIdx << ":" << SC.Name << " on " << InstRWDef->getValueAsDef("SchedModel")->getName() << "\n"); diff --git a/llvm/utils/TableGen/CodeGenSchedule.h b/llvm/utils/TableGen/CodeGenSchedule.h index 3265cfb..2d906bb 100644 --- a/llvm/utils/TableGen/CodeGenSchedule.h +++ b/llvm/utils/TableGen/CodeGenSchedule.h @@ -139,7 +139,8 @@ struct CodeGenSchedClass { // off to join another inferred class. RecVec InstRWs; - CodeGenSchedClass(): Index(0), ItinClassDef(nullptr) {} + CodeGenSchedClass(unsigned Index, std::string Name, Record *ItinClassDef) + : Index(Index), Name(std::move(Name)), ItinClassDef(ItinClassDef) {} bool isKeyEqual(Record *IC, ArrayRef W, ArrayRef R) const { @@ -198,9 +199,9 @@ struct CodeGenProcModel { // Per-operand machine model resources associated with this processor. RecVec ProcResourceDefs; - CodeGenProcModel(unsigned Idx, const std::string &Name, Record *MDef, + CodeGenProcModel(unsigned Idx, std::string Name, Record *MDef, Record *IDef) : - Index(Idx), ModelName(Name), ModelDef(MDef), ItinsDef(IDef) {} + Index(Idx), ModelName(std::move(Name)), ModelDef(MDef), ItinsDef(IDef) {} bool hasItineraries() const { return !ItinsDef->getValueAsListOfDefs("IID").empty(); -- 2.7.4