From 2738eddf4ad7aded6760466dff36b15e6503050d Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Sat, 18 Jan 2020 07:23:49 +0800 Subject: [PATCH] [VTA][TSIM] Enable TSIM CI Testing (#4407) * Update task_python_vta.sh * install sbt=1.1.1 with apt-get * update verilator_opt * install verilator with major version 4.0 * disable multi-threading for now * bug fix for correcting uop fetch address in LoadUop module * bug fix for correcting uop fetch address in LoadUop module * adjustment to read from dram_offset * enable USE_THREADS with verilator 4.x * DEBUG: try avoid core dump with verilator 4.x * bug fix in LoadUop module * log mega cycles in tsim * download cat.png to avoid fetching in each run * bug fix in LoadUop module * solve dram_even/sram_even issue * bug fix * introduce scalalint in ci * speedup tsim in ci * bug fix * lint scala code before building * disable multi-threading * split fsim/tsim script * update Jenkins settings * duplicate task_python_vta_fsim.sh as task_python_vta.sh for now Co-authored-by: Thierry Moreau --- Makefile | 7 +++-- tests/scripts/task_python_vta.sh | 20 ++---------- tests/scripts/task_python_vta_fsim.sh | 20 ++---------- tests/scripts/task_python_vta_tsim.sh | 36 ++++++++++------------ vta/hardware/chisel/Makefile | 2 +- .../chisel/src/main/scala/core/LoadUop.scala | 16 +++++++--- vta/hardware/dpi/tsim_device.cc | 2 ++ vta/tutorials/frontend/deploy_vision_on_vta.py | 5 +-- 8 files changed, 45 insertions(+), 63 deletions(-) diff --git a/Makefile b/Makefile index d34fbe4..ad24baa 100644 --- a/Makefile +++ b/Makefile @@ -17,7 +17,7 @@ ROOTDIR = $(CURDIR) -.PHONY: clean all test doc pylint cpplint lint\ +.PHONY: clean all test doc pylint cpplint scalalint lint\ cython cython2 cython3 web runtime vta ifndef DMLC_CORE_PATH @@ -80,7 +80,10 @@ pylint: jnilint: python3 3rdparty/dmlc-core/scripts/lint.py tvm4j-jni cpp jvm/native/src -lint: cpplint pylint jnilint +scalalint: + make -C vta/hardware/chisel lint + +lint: cpplint pylint jnilint scalalint doc: doxygen docs/Doxyfile diff --git a/tests/scripts/task_python_vta.sh b/tests/scripts/task_python_vta.sh index 1e5055e..a6bfb1c 100755 --- a/tests/scripts/task_python_vta.sh +++ b/tests/scripts/task_python_vta.sh @@ -29,6 +29,9 @@ rm -rf ~/.tvm # Rebuild cython make cython3 +# Reset default fsim simulation +cp vta/config/fsim_sample.json vta/config/vta_config.json + # Run unit tests in functional/fast simulator echo "Running unittest in fsim..." python3 -m pytest -v vta/tests/python/unittest @@ -36,20 +39,3 @@ python3 -m pytest -v vta/tests/python/unittest # Run unit tests in functional/fast simulator echo "Running integration test in fsim..." python3 -m pytest -v vta/tests/python/integration - -# # Build VTA chisel design and verilator simulator -# (make -C vta/hardware/chisel/) - -# # Set default VTA config to use TSIM cycle accurate sim -# cp vta/config/tsim_sample.json vta/config/vta_config.json - -# # Run unit tests in cycle accurate simulator -# echo "Running unittest in tsim..." -# python3 -m pytest -v vta/tests/python/unittest - -# # Run unit tests in cycle accurate simulator -# echo "Running integration test in tsim..." -# python3 -m pytest -v vta/tests/python/integration - -# # Reset default fsim simulation -# cp vta/config/fsim_sample.json vta/config/vta_config.json diff --git a/tests/scripts/task_python_vta_fsim.sh b/tests/scripts/task_python_vta_fsim.sh index 1e5055e..a6bfb1c 100755 --- a/tests/scripts/task_python_vta_fsim.sh +++ b/tests/scripts/task_python_vta_fsim.sh @@ -29,6 +29,9 @@ rm -rf ~/.tvm # Rebuild cython make cython3 +# Reset default fsim simulation +cp vta/config/fsim_sample.json vta/config/vta_config.json + # Run unit tests in functional/fast simulator echo "Running unittest in fsim..." python3 -m pytest -v vta/tests/python/unittest @@ -36,20 +39,3 @@ python3 -m pytest -v vta/tests/python/unittest # Run unit tests in functional/fast simulator echo "Running integration test in fsim..." python3 -m pytest -v vta/tests/python/integration - -# # Build VTA chisel design and verilator simulator -# (make -C vta/hardware/chisel/) - -# # Set default VTA config to use TSIM cycle accurate sim -# cp vta/config/tsim_sample.json vta/config/vta_config.json - -# # Run unit tests in cycle accurate simulator -# echo "Running unittest in tsim..." -# python3 -m pytest -v vta/tests/python/unittest - -# # Run unit tests in cycle accurate simulator -# echo "Running integration test in tsim..." -# python3 -m pytest -v vta/tests/python/integration - -# # Reset default fsim simulation -# cp vta/config/fsim_sample.json vta/config/vta_config.json diff --git a/tests/scripts/task_python_vta_tsim.sh b/tests/scripts/task_python_vta_tsim.sh index 1e5055e..eba62e5 100755 --- a/tests/scripts/task_python_vta_tsim.sh +++ b/tests/scripts/task_python_vta_tsim.sh @@ -29,27 +29,25 @@ rm -rf ~/.tvm # Rebuild cython make cython3 -# Run unit tests in functional/fast simulator -echo "Running unittest in fsim..." -python3 -m pytest -v vta/tests/python/unittest - -# Run unit tests in functional/fast simulator -echo "Running integration test in fsim..." -python3 -m pytest -v vta/tests/python/integration +# Set default VTA config to use TSIM cycle accurate sim +cp vta/config/tsim_sample.json vta/config/vta_config.json -# # Build VTA chisel design and verilator simulator -# (make -C vta/hardware/chisel/) +# Check style of scala code +echo "Check style of scala code..." +make -C vta/hardware/chisel lint -# # Set default VTA config to use TSIM cycle accurate sim -# cp vta/config/tsim_sample.json vta/config/vta_config.json +# Build VTA chisel design and verilator simulator +echo "Building VTA chisel design..." +make -C vta/hardware/chisel cleanall +make -C vta/hardware/chisel USE_THREADS=0 lib -# # Run unit tests in cycle accurate simulator -# echo "Running unittest in tsim..." -# python3 -m pytest -v vta/tests/python/unittest +# Run unit tests in cycle accurate simulator +echo "Running unittest in tsim..." +python3 -m pytest -v vta/tests/python/unittest -# # Run unit tests in cycle accurate simulator -# echo "Running integration test in tsim..." -# python3 -m pytest -v vta/tests/python/integration +# Run unit tests in cycle accurate simulator +echo "Running integration test in tsim..." +python3 -m pytest -v vta/tests/python/integration -# # Reset default fsim simulation -# cp vta/config/fsim_sample.json vta/config/vta_config.json +# Reset default fsim simulation +cp vta/config/fsim_sample.json vta/config/vta_config.json diff --git a/vta/hardware/chisel/Makefile b/vta/hardware/chisel/Makefile index 743f6c6..a98c52c 100644 --- a/vta/hardware/chisel/Makefile +++ b/vta/hardware/chisel/Makefile @@ -94,7 +94,7 @@ else endif ifneq ($(USE_THREADS), 0) - verilator_opt += -threads $(USE_THREADS) + verilator_opt += --threads $(USE_THREADS) cxx_flags += -DVL_THREADED cxx_objs += $(verilator_build_dir)/verilated_threads.o endif diff --git a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala index 3432ec6..c7d0f44 100644 --- a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala +++ b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala @@ -81,7 +81,8 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { val xmax = (1 << mp.lenBits).U val xmax_bytes = ((1 << mp.lenBits) * mp.dataBits / 8).U - val offsetIsEven = (dec.sram_offset % 2.U) === 0.U + val dram_even = (dec.dram_offset % 2.U) === 0.U + val sram_even = (dec.sram_offset % 2.U) === 0.U val sizeIsEven = (dec.xsize % 2.U) === 0.U val sIdle :: sReadCmd :: sReadData :: Nil = Enum(3) @@ -129,11 +130,10 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { // read-from-dram val maskOffset = VecInit(Seq.fill(M_DRAM_OFFSET_BITS)(true.B)).asUInt when(state === sIdle) { - when(offsetIsEven) { + when(dram_even) { raddr := io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(uopBytes))) }.otherwise { - raddr := (io.baddr | (maskOffset & (dec.dram_offset << log2Ceil( - uopBytes)))) - uopBytes.U + raddr := (io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(uopBytes)))) - uopBytes.U } }.elsewhen(state === sReadData && xcnt === xlen && xrem =/= 0.U) { raddr := raddr + xmax_bytes @@ -162,7 +162,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { val mem = SyncReadMem(uopDepth, chiselTypeOf(wdata)) val wmask = Reg(Vec(numUop, Bool())) - when(offsetIsEven) { + when(sram_even) { when(sizeIsEven) { wmask := "b_11".U.asTypeOf(wmask) }.elsewhen(io.vme_rd.cmd.fire()) { @@ -192,6 +192,12 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { } wdata := io.vme_rd.data.bits.asTypeOf(wdata) + when(dram_even === false.B && sram_even) { + wdata(0) := io.vme_rd.data.bits.asTypeOf(wdata)(1) + }.elsewhen(sram_even === false.B && dram_even) { + wdata(1) := io.vme_rd.data.bits.asTypeOf(wdata)(0) + } + when(io.vme_rd.data.fire()) { mem.write(waddr, wdata, wmask) } diff --git a/vta/hardware/dpi/tsim_device.cc b/vta/hardware/dpi/tsim_device.cc index 1dae273..d197fbd 100644 --- a/vta/hardware/dpi/tsim_device.cc +++ b/vta/hardware/dpi/tsim_device.cc @@ -141,6 +141,8 @@ int VTADPISim() { tfp->dump(static_cast(trace_count * 2 + 1)); #endif trace_count++; + if ((trace_count % 1000000) == 1) + fprintf(stderr, "[traced %dM cycles]\n", trace_count / 1000000); while (top->sim_wait) { top->clock = 0; std::this_thread::sleep_for(std::chrono::milliseconds(100)); diff --git a/vta/tutorials/frontend/deploy_vision_on_vta.py b/vta/tutorials/frontend/deploy_vision_on_vta.py index 47773bd..154eb85 100644 --- a/vta/tutorials/frontend/deploy_vision_on_vta.py +++ b/vta/tutorials/frontend/deploy_vision_on_vta.py @@ -225,10 +225,11 @@ synset = eval(open(categ_fn).read()) # Download test image image_url = 'https://homes.cs.washington.edu/~moreau/media/vta/cat.jpg' -response = requests.get(image_url) +image_fn = 'cat.png' +download.download(image_url, image_fn) # Prepare test image for inference -image = Image.open(BytesIO(response.content)).resize((224, 224)) +image = Image.open(image_fn).resize((224, 224)) plt.imshow(image) plt.show() image = np.array(image) - np.array([123., 117., 104.]) -- 2.7.4