From 272d35aef5e0d32f12b700ea12c608e0323ceb3f Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 15 Feb 2020 23:15:52 -0800 Subject: [PATCH] [X86] Separate floating point handling out of EmitCmp and emitFlagsForSetcc. Both of those functions only have a single caller starting at LowerSETCC. Just handle floating point directly in LowerSETCC. This removes the need to pass Chain and IsSignaling all the way down. --- llvm/lib/Target/X86/X86ISelLowering.cpp | 76 ++++++++++++++++----------------- llvm/lib/Target/X86/X86ISelLowering.h | 3 +- 2 files changed, 38 insertions(+), 41 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 5702d7b..e6e2a81 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -21152,27 +21152,14 @@ static SDValue EmitTest(SDValue Op, unsigned X86CC, const SDLoc &dl, /// Emit nodes that will be selected as "cmp Op0,Op1", or something /// equivalent. -static std::pair EmitCmp(SDValue Op0, SDValue Op1, - unsigned X86CC, const SDLoc &dl, - SelectionDAG &DAG, - const X86Subtarget &Subtarget, - SDValue Chain, bool IsSignaling) { +static SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, + const SDLoc &dl, SelectionDAG &DAG, + const X86Subtarget &Subtarget) { if (isNullConstant(Op1)) - return std::make_pair(EmitTest(Op0, X86CC, dl, DAG, Subtarget), Chain); + return EmitTest(Op0, X86CC, dl, DAG, Subtarget); EVT CmpVT = Op0.getValueType(); - if (CmpVT.isFloatingPoint()) { - if (Chain) { - SDValue Res = - DAG.getNode(IsSignaling ? X86ISD::STRICT_FCMPS : X86ISD::STRICT_FCMP, - dl, {MVT::i32, MVT::Other}, {Chain, Op0, Op1}); - return std::make_pair(Res, Res.getValue(1)); - } - return std::make_pair(DAG.getNode(X86ISD::FCMP, dl, MVT::i32, Op0, Op1), - SDValue()); - } - assert((CmpVT == MVT::i8 || CmpVT == MVT::i16 || CmpVT == MVT::i32 || CmpVT == MVT::i64) && "Unexpected VT!"); @@ -21225,7 +21212,7 @@ static std::pair EmitCmp(SDValue Op0, SDValue Op1, // Use SUB instead of CMP to enable CSE between SUB and CMP. SDVTList VTs = DAG.getVTList(CmpVT, MVT::i32); SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs, Op0, Op1); - return std::make_pair(Sub.getValue(1), SDValue()); + return Sub.getValue(1); } /// Check if replacement of SQRT with RSQRT should be disabled. @@ -22135,9 +22122,8 @@ static SDValue EmitAVX512Test(SDValue Op0, SDValue Op1, ISD::CondCode CC, /// corresponding X86 condition code constant in X86CC. SDValue X86TargetLowering::emitFlagsForSetcc(SDValue Op0, SDValue Op1, ISD::CondCode CC, const SDLoc &dl, - SelectionDAG &DAG, SDValue &X86CC, - SDValue &Chain, - bool IsSignaling) const { + SelectionDAG &DAG, + SDValue &X86CC) const { // Optimize to BT if possible. // Lower (X & (1 << N)) == 0 to BT(X, N). // Lower ((X >>u N) & 1) != 0 to BT(X, N). @@ -22196,16 +22182,11 @@ SDValue X86TargetLowering::emitFlagsForSetcc(SDValue Op0, SDValue Op1, } } - bool IsFP = Op1.getSimpleValueType().isFloatingPoint(); - X86::CondCode CondCode = TranslateX86CC(CC, dl, IsFP, Op0, Op1, DAG); - if (CondCode == X86::COND_INVALID) - return SDValue(); + X86::CondCode CondCode = + TranslateX86CC(CC, dl, /*IsFP*/ false, Op0, Op1, DAG); + assert(CondCode != X86::COND_INVALID && "Unexpected condition code!"); - std::pair Tmp = - EmitCmp(Op0, Op1, CondCode, dl, DAG, Subtarget, Chain, IsSignaling); - SDValue EFLAGS = Tmp.first; - if (Chain) - Chain = Tmp.second; + SDValue EFLAGS = EmitCmp(Op0, Op1, CondCode, dl, DAG, Subtarget); X86CC = DAG.getTargetConstant(CondCode, dl, MVT::i8); return EFLAGS; } @@ -22242,18 +22223,35 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { } } - SDValue X86CC; - SDValue EFLAGS = emitFlagsForSetcc(Op0, Op1, CC, dl, DAG, X86CC, Chain, - Op.getOpcode() == ISD::STRICT_FSETCCS); - if (!EFLAGS) - return SDValue(); + if (Op0.getSimpleValueType().isInteger()) { + SDValue X86CC; + SDValue EFLAGS = emitFlagsForSetcc(Op0, Op1, CC, dl, DAG, X86CC); + if (!EFLAGS) + return SDValue(); - SDValue Res = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, X86CC, EFLAGS); + SDValue Res = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, X86CC, EFLAGS); + return IsStrict ? DAG.getMergeValues({Res, Chain}, dl) : Res; + } - if (IsStrict) - return DAG.getMergeValues({Res, Chain}, dl); + // Handle floating point. + X86::CondCode CondCode = TranslateX86CC(CC, dl, /*IsFP*/ true, Op0, Op1, DAG); + if (CondCode == X86::COND_INVALID) + return SDValue(); - return Res; + SDValue EFLAGS; + if (IsStrict) { + bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; + EFLAGS = + DAG.getNode(IsSignaling ? X86ISD::STRICT_FCMPS : X86ISD::STRICT_FCMP, + dl, {MVT::i32, MVT::Other}, {Chain, Op0, Op1}); + Chain = EFLAGS.getValue(1); + } else { + EFLAGS = DAG.getNode(X86ISD::FCMP, dl, MVT::i32, Op0, Op1); + } + + SDValue X86CC = DAG.getTargetConstant(CondCode, dl, MVT::i8); + SDValue Res = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, X86CC, EFLAGS); + return IsStrict ? DAG.getMergeValues({Res, Chain}, dl) : Res; } SDValue X86TargetLowering::LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const { diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index d570df2..4e45c84 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -1492,8 +1492,7 @@ namespace llvm { /// corresponding X86 condition code constant in X86CC. SDValue emitFlagsForSetcc(SDValue Op0, SDValue Op1, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG, - SDValue &X86CC, SDValue &Chain, - bool IsSignaling) const; + SDValue &X86CC) const; /// Check if replacement of SQRT with RSQRT should be disabled. bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override; -- 2.7.4