From 27050395d21955cf91f70a10da7abb726fa0bf70 Mon Sep 17 00:00:00 2001
From: "Xiang, Haihao" <haihao.xiang@intel.com>
Date: Fri, 10 Jun 2011 16:04:30 +0800
Subject: [PATCH] Support DP for sampler/render/constant/data cache

Since Sandybridge, DP supports cache select for read/write. Some write messages such as
OWord Block Write don't support render cache any more on Ivybridge. So introduce a
generic data_port messsage for Sandybridge+.

    data_port(
        cache_type,   /* sampler, render, constant or data(on Ivybridge+) cache */
        message_type, /* read or write type */
        message_control,
        binding_table_index,
        write_commit_or_category, /* write commit on Sandybridge, category on Ivybridge+ */
        header_present)

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
---
 assembler/src/brw_defines.h |  1 +
 assembler/src/brw_structs.h | 15 ++++++++++++++-
 assembler/src/gram.y        | 39 ++++++++++++++++++++++++++++++++++++++-
 assembler/src/lex.l         |  1 +
 4 files changed, 54 insertions(+), 2 deletions(-)

diff --git a/assembler/src/brw_defines.h b/assembler/src/brw_defines.h
index aba1b99..0a6f4c4 100644
--- a/assembler/src/brw_defines.h
+++ b/assembler/src/brw_defines.h
@@ -711,6 +711,7 @@
 #define BRW_MESSAGE_TARGET_THREAD_SPAWNER     7
 #define BRW_MESSAGE_TARGET_VME                8
 #define BRW_MESSAGE_TARGET_DP_CC              9  /* data port constant cache */
+#define BRW_MESSAGE_TARGET_DP_DC              10 /* data port data cache */
 
 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32     0
 #define BRW_SAMPLER_RETURN_FORMAT_UINT32      2
diff --git a/assembler/src/brw_structs.h b/assembler/src/brw_structs.h
index 045b729..e3b66d9 100644
--- a/assembler/src/brw_structs.h
+++ b/assembler/src/brw_structs.h
@@ -1455,14 +1455,27 @@ struct brw_instruction
 
        struct {
            GLuint binding_table_index:8;
-           GLuint msg_control:6;
+           GLuint msg_control:5;
            GLuint msg_type:4;    
+           GLuint send_commit_msg:1; /* ignore on read message */
            GLuint pad0:1;
            GLuint header_present:1;
            GLuint response_length:5;
            GLuint msg_length:4;
            GLuint pad1:2;
            GLuint end_of_thread:1;
+       } dp_gen6;
+
+       struct {
+           GLuint binding_table_index:8;
+           GLuint msg_control:6;
+           GLuint msg_type:4;    
+           GLuint category:1;
+           GLuint header_present:1;
+           GLuint response_length:5;
+           GLuint msg_length:4;
+           GLuint pad1:2;
+           GLuint end_of_thread:1;
        } dp_gen7;
 
        struct {
diff --git a/assembler/src/gram.y b/assembler/src/gram.y
index 8e2249c..6c98a61 100644
--- a/assembler/src/gram.y
+++ b/assembler/src/gram.y
@@ -111,7 +111,7 @@ void set_direct_src_operand(struct src_operand *src, struct direct_reg *reg,
 %token <integer> PUSH MREST POP WAIT DO ENDIF ILLEGAL
 %token <integer> MATH_INST
 
-%token NULL_TOKEN MATH SAMPLER GATEWAY READ WRITE URB THREAD_SPAWNER VME
+%token NULL_TOKEN MATH SAMPLER GATEWAY READ WRITE URB THREAD_SPAWNER VME DATA_PORT
 
 %token MSGLEN RETURNLEN
 %token <integer> ALLOCATE USED COMPLETE TRANSPOSE INTERLEAVE
@@ -1212,6 +1212,43 @@ msgtarget:	NULL_TOKEN
                       YYERROR;
 		  }    
 		} 
+
+		| DATA_PORT LPAREN INTEGER COMMA INTEGER COMMA INTEGER COMMA 
+                INTEGER COMMA INTEGER COMMA INTEGER RPAREN
+		{
+                    $$.bits2.send_gen5.sfid = $3;
+                    $$.bits3.generic_gen5.header_present = ($13 != 0);
+
+                    if (gen_level >= 7) {
+                        if ($3 != BRW_MESSAGE_TARGET_DP_SC &&
+                            $3 != BRW_MESSAGE_TARGET_DP_RC &&
+                            $3 != BRW_MESSAGE_TARGET_DP_CC &&
+                            $3 != BRW_MESSAGE_TARGET_DP_DC) {
+                            fprintf (stderr, "error: wrong cache type\n");
+                            YYERROR;
+                        }
+
+                        $$.bits3.dp_gen7.category = $11;
+                        $$.bits3.dp_gen7.binding_table_index = $9;
+                        $$.bits3.dp_gen7.msg_control = $7;
+                        $$.bits3.dp_gen7.msg_type = $5;
+                    } else if (gen_level == 6) {
+                        if ($3 != BRW_MESSAGE_TARGET_DP_SC &&
+                            $3 != BRW_MESSAGE_TARGET_DP_RC &&
+                            $3 != BRW_MESSAGE_TARGET_DP_CC) {
+                            fprintf (stderr, "error: wrong cache type\n");
+                            YYERROR;
+                        }
+
+                        $$.bits3.dp_gen6.send_commit_msg = $11;
+                        $$.bits3.dp_gen6.binding_table_index = $9;
+                        $$.bits3.dp_gen6.msg_control = $7;
+                        $$.bits3.dp_gen6.msg_type = $5;
+                    } else if (gen_level < 5) {
+                        fprintf (stderr, "Gen6- donesn't support data port for sampler/render/constant/data cache\n");
+                        YYERROR;
+                    }
+		} 
 ;
 
 urb_allocate:	ALLOCATE { $$ = 1; }
diff --git a/assembler/src/lex.l b/assembler/src/lex.l
index 910b555..ec1fc13 100644
--- a/assembler/src/lex.l
+++ b/assembler/src/lex.l
@@ -137,6 +137,7 @@ yylval.integer = BRW_CHANNEL_W;
 "urb" { return URB; }
 "thread_spawner" { return THREAD_SPAWNER; }
 "vme" { return VME; }
+"data_port" { return DATA_PORT; }
 
 "allocate" { return ALLOCATE; }
 "used" { return USED; }
-- 
2.7.4