From 26fb036559d05b601a585c751177d6ec367fb65b Mon Sep 17 00:00:00 2001 From: Jessica Paquette Date: Wed, 17 Feb 2021 11:35:46 -0800 Subject: [PATCH] [GlobalISel] Implement computeNumSignBits for G_ASSERT_SEXT Same implementation as G_SEXT_INREG. Add a testcase to combine-sext-inreg for a concrete example, and a testcase to KnownBitsTest. Differential Revision: https://reviews.llvm.org/D96897 --- llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp | 1 + .../AMDGPU/GlobalISel/combine-sext-inreg.mir | 33 +++++++++++ .../unittests/CodeGen/GlobalISel/KnownBitsTest.cpp | 69 ++++++++++++++++++++++ 3 files changed, 103 insertions(+) diff --git a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp index 53e8b34a..3d8b298 100644 --- a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp +++ b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp @@ -531,6 +531,7 @@ unsigned GISelKnownBits::computeNumSignBits(Register R, unsigned Tmp = DstTy.getScalarSizeInBits() - SrcTy.getScalarSizeInBits(); return computeNumSignBits(Src, DemandedElts, Depth + 1) + Tmp; } + case TargetOpcode::G_ASSERT_SEXT: case TargetOpcode::G_SEXT_INREG: { // Max of the input and what this extends. Register Src = MI.getOperand(1).getReg(); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir index 578845b..45b6820 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir @@ -337,3 +337,36 @@ body: | $vgpr0 = COPY %8 ... +--- +name: assert_sext_s8 +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0 + ; GCN-LABEL: name: assert_sext_s8 + ; GCN: liveins: $vgpr0 + ; GCN: %copy:_(s32) = COPY $vgpr0 + ; GCN: %assert_sext:_(s32) = G_ASSERT_SEXT %copy, 8 + ; GCN: $vgpr0 = COPY %assert_sext(s32) + %copy:_(s32) = COPY $vgpr0 + %assert_sext:_(s32) = G_ASSERT_SEXT %copy, 8 + %sext_inreg:_(s32) = G_SEXT_INREG %assert_sext, 8 + $vgpr0 = COPY %sext_inreg + +... +--- +name: sext_inreg_s7_assert_sext_s8 +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0 + ; GCN-LABEL: name: sext_inreg_s7_assert_sext_s8 + ; GCN: liveins: $vgpr0 + ; GCN: %copy:_(s32) = COPY $vgpr0 + ; GCN: %assert_sext:_(s32) = G_ASSERT_SEXT %copy, 8 + ; GCN: %sext_inreg:_(s32) = G_SEXT_INREG %assert_sext, 7 + ; GCN: $vgpr0 = COPY %sext_inreg(s32) + %copy:_(s32) = COPY $vgpr0 + %assert_sext:_(s32) = G_ASSERT_SEXT %copy, 8 + %sext_inreg:_(s32) = G_SEXT_INREG %assert_sext, 7 + $vgpr0 = COPY %sext_inreg diff --git a/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp b/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp index 25b8f48..5b365a5 100644 --- a/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp +++ b/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp @@ -437,6 +437,75 @@ TEST_F(AArch64GISelMITest, TestNumSignBitsSextInReg) { EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext)); } +TEST_F(AArch64GISelMITest, TestNumSignBitsAssertSext) { + StringRef MIRString = R"( + %ptr:_(p0) = G_IMPLICIT_DEF + %load4:_(s32) = G_LOAD %ptr :: (load 4) + + %assert_sext1:_(s32) = G_ASSERT_SEXT %load4, 1 + %copy_assert_sext1:_(s32) = COPY %assert_sext1 + + %assert_sext7:_(s32) = G_ASSERT_SEXT %load4, 7 + %copy_assert_sext7:_(s32) = COPY %assert_sext7 + + %assert_sext8:_(s32) = G_ASSERT_SEXT %load4, 8 + %copy_assert_sext8:_(s32) = COPY %assert_sext8 + + %assert_sext9:_(s32) = G_ASSERT_SEXT %load4, 9 + %copy_assert_sext9:_(s32) = COPY %assert_sext9 + + %assert_sext31:_(s32) = G_ASSERT_SEXT %load4, 31 + %copy_assert_sext31:_(s32) = COPY %assert_sext31 + + %load1:_(s8) = G_LOAD %ptr :: (load 1) + %sext_load1:_(s32) = G_SEXT %load1 + + %assert_sext6_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 6 + %copy_assert_sext6_sext:_(s32) = COPY %assert_sext6_sext + + %assert_sext7_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 7 + %copy_assert_sext7_sext:_(s32) = COPY %assert_sext7_sext + + %assert_sext8_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 8 + %copy_assert_sext8_sext:_(s32) = COPY %assert_sext8_sext + + %assert_sext9_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 9 + %copy_assert_sext9_sext:_(s32) = COPY %assert_sext9_sext + + %assert_sext31_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 31 + %copy_assert_sext31_sext:_(s32) = COPY %assert_sext31_sext +)"; + + setUp(MIRString); + if (!TM) + return; + + Register CopyInReg1 = Copies[Copies.size() - 10]; + Register CopyInReg7 = Copies[Copies.size() - 9]; + Register CopyInReg8 = Copies[Copies.size() - 8]; + Register CopyInReg9 = Copies[Copies.size() - 7]; + Register CopyInReg31 = Copies[Copies.size() - 6]; + + Register CopyInReg6Sext = Copies[Copies.size() - 5]; + Register CopyInReg7Sext = Copies[Copies.size() - 4]; + Register CopyInReg8Sext = Copies[Copies.size() - 3]; + Register CopyInReg9Sext = Copies[Copies.size() - 2]; + Register CopyInReg31Sext = Copies[Copies.size() - 1]; + + GISelKnownBits Info(*MF); + EXPECT_EQ(32u, Info.computeNumSignBits(CopyInReg1)); + EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7)); + EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8)); + EXPECT_EQ(24u, Info.computeNumSignBits(CopyInReg9)); + EXPECT_EQ(2u, Info.computeNumSignBits(CopyInReg31)); + + EXPECT_EQ(27u, Info.computeNumSignBits(CopyInReg6Sext)); + EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7Sext)); + EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8Sext)); + EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg9Sext)); + EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext)); +} + TEST_F(AArch64GISelMITest, TestNumSignBitsTrunc) { StringRef MIRString = " %3:_(p0) = G_IMPLICIT_DEF\n" " %4:_(s32) = G_LOAD %3 :: (load 4)\n" -- 2.7.4