From 26c57f1723fe68a50e5eceeac911c7b7528c1700 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 9 Feb 2014 17:31:47 -0300 Subject: [PATCH] upstream: [media] mt9p031: Add support for PLL bypass When the input clock frequency is out of bounds for the PLL, bypass the PLL and just divide the input clock to achieve the requested output frequency. Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/mt9p031.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index 8ead96c..e80ea65 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -272,6 +272,21 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) return 0; } + /* If the external clock frequency is out of bounds for the PLL use the + * pixel clock divider only and disable the PLL. + */ + if (pdata->ext_freq > limits.ext_clock_max) { + unsigned int div; + + div = DIV_ROUND_UP(pdata->ext_freq, pdata->target_freq); + div = roundup_pow_of_two(div) / 2; + + mt9p031->clk_div = max_t(unsigned int, div, 64); + mt9p031->use_pll = false; + + return 0; + } + mt9p031->pll.ext_clock = pdata->ext_freq; mt9p031->pll.pix_clock = pdata->target_freq; mt9p031->use_pll = true; -- 2.7.4