From 26a7e997fb141cd15788af64eb228dc138cec2a7 Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Tue, 20 Jun 2023 21:35:07 -0700 Subject: [PATCH] iris: Add CCS cache flush bits Signed-off-by: Sagar Ghuge Reviewed-by: Lionel Landwerlin Part-of: --- src/gallium/drivers/iris/iris_context.h | 1 + src/gallium/drivers/iris/iris_state.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h index 1c850de..8bcfa8e 100644 --- a/src/gallium/drivers/iris/iris_context.h +++ b/src/gallium/drivers/iris/iris_context.h @@ -358,6 +358,7 @@ enum pipe_control_flags PIPE_CONTROL_PSS_STALL_SYNC = (1 << 27), PIPE_CONTROL_L3_READ_ONLY_CACHE_INVALIDATE = (1 << 28), PIPE_CONTROL_UNTYPED_DATAPORT_CACHE_FLUSH = (1 << 29), + PIPE_CONTROL_CCS_CACHE_FLUSH = (1 << 30), }; #define PIPE_CONTROL_CACHE_FLUSH_BITS \ diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index e27274c..adafa21 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -8688,7 +8688,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, if (INTEL_DEBUG(DEBUG_PIPE_CONTROL)) { fprintf(stderr, - " PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64"]: %s\n", + " PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64"]: %s\n", (flags & PIPE_CONTROL_FLUSH_ENABLE) ? "PipeCon " : "", (flags & PIPE_CONTROL_CS_STALL) ? "CS " : "", (flags & PIPE_CONTROL_STALL_AT_SCOREBOARD) ? "Scoreboard " : "", @@ -8699,6 +8699,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, (flags & PIPE_CONTROL_DATA_CACHE_FLUSH) ? "DC " : "", (flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH) ? "ZFlush " : "", (flags & PIPE_CONTROL_TILE_CACHE_FLUSH) ? "Tile " : "", + (flags & PIPE_CONTROL_CCS_CACHE_FLUSH) ? "CCS " : "", (flags & PIPE_CONTROL_DEPTH_STALL) ? "ZStall " : "", (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE) ? "State " : "", (flags & PIPE_CONTROL_TLB_INVALIDATE) ? "TLB " : "", @@ -8742,6 +8743,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, (flags & PIPE_CONTROL_UNTYPED_DATAPORT_CACHE_FLUSH) && IS_COMPUTE_PIPELINE(batch); pc.HDCPipelineFlushEnable |= pc.UntypedDataPortCacheFlushEnable; + pc.CCSFlushEnable |= flags & PIPE_CONTROL_CCS_CACHE_FLUSH; #endif pc.LRIPostSyncOperation = NoLRIOperation; pc.PipeControlFlushEnable = flags & PIPE_CONTROL_FLUSH_ENABLE; -- 2.7.4