From 26a22478cdfe6fe4d169320910c38958d5dafc38 Mon Sep 17 00:00:00 2001 From: Ties Stuij Date: Wed, 8 Jul 2020 13:12:30 +0100 Subject: [PATCH] [CodeGen] Don't combine extract + concat vectors with non-legal types Summary: The following combine currently breaks in the DAGCombiner: ``` extract_vector_elt (concat_vectors v4i16:a, v4i16:b), x -> extract_vector_elt a, x ``` This happens because after we have combined these nodes we have inserted nodes that use individual instances of the vector element type. In the above example i16. However this isn't a legal type on all backends, and when the combining pass calls the legalizer it breaks as it expects types to already be legal. The type legalizer has already been run, and running it again would make a mess of the nodes. In the example code at least, the generated code is still efficient after the change. Reviewers: miyuki, arsenm, dmgreen, lebedev.ri Reviewed By: miyuki, lebedev.ri Subscribers: lebedev.ri, wdng, hiraditya, steven.zhang, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D83231 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 7 +++++-- .../CodeGen/AArch64/regress-combine-extract-vectors.ll | 17 +++++++++++++++++ 2 files changed, 22 insertions(+), 2 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/regress-combine-extract-vectors.ll diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 4042a81..a1d5769 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -17843,8 +17843,11 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { Elt = (Idx < (int)NumElts) ? Idx : Idx - (int)NumElts; Index = DAG.getConstant(Elt, DL, Index.getValueType()); } - } else if (VecOp.getOpcode() == ISD::CONCAT_VECTORS && - !BCNumEltsChanged && VecVT.getVectorElementType() == ScalarVT) { + } else if (VecOp.getOpcode() == ISD::CONCAT_VECTORS && !BCNumEltsChanged && + VecVT.getVectorElementType() == ScalarVT && + (!LegalTypes || + TLI.isTypeLegal( + VecOp.getOperand(0).getValueType().getVectorElementType()))) { // extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 0 // -> extract_vector_elt a, 0 // extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 1 diff --git a/llvm/test/CodeGen/AArch64/regress-combine-extract-vectors.ll b/llvm/test/CodeGen/AArch64/regress-combine-extract-vectors.ll new file mode 100644 index 0000000..1662e27 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/regress-combine-extract-vectors.ll @@ -0,0 +1,17 @@ +; RUN: llc -asm-verbose=0 -mtriple aarch64-arm-none-eabi < %s | FileCheck %s + +; The following code previously broke in the DAGCombiner. Specifically, trying to combine: +; extract_vector_elt (concat_vectors v4i16:a, v4i16:b), x +; -> extract_vector_elt a, x + +define half @test_combine_extract_concat_vectors(<4 x i16> %a) nounwind { +entry: + %0 = shufflevector <4 x i16> %a, <4 x i16> undef, <8 x i32> + %1 = bitcast <8 x i16> %0 to <8 x half> + %2 = extractelement <8 x half> %1, i32 3 + ret half %2 +} + +; CHECK-LABEL: test_combine_extract_concat_vectors: +; CHECK-NEXT: mov h0, v0.h[3] +; CHECK-NEXT: ret -- 2.7.4