From 264cf37348faec3230c58c5b1c1215386484ebd9 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 19 May 2023 03:09:53 -0400 Subject: [PATCH] radeonsi: re-enable fp16_rtz for compute blits to fix PBO tests on gfx11 Fixes: bcdde99675d27 - radeonsi: don't convert to fp16 in the compute blit if not testing Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_compute_blit.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c index c8c6c19..abb14e7 100644 --- a/src/gallium/drivers/radeonsi/si_compute_blit.c +++ b/src/gallium/drivers/radeonsi/si_compute_blit.c @@ -1140,14 +1140,15 @@ bool si_compute_blit(struct si_context *sctx, const struct pipe_blit_info *info, options.last_src_channel < options.last_dst_channel && options.last_dst_channel == 3; - /* WARNING: We only use this codepath for AMD_TEST to get results identical with the gfx blit, + /* WARNING: We need this option for AMD_TEST to get results identical with the gfx blit, * otherwise we wouldn't be able to fully validate whether everything else works. * The test expects that the behavior is identical to u_blitter. + * + * Additionally, we need to keep this enabled even when not testing because not doing fp16_rtz + * breaks "piglit/bin/texsubimage -auto pbo". */ - if (testing) { - options.fp16_rtz = !util_format_is_pure_integer(info->dst.format) && - dst_desc->channel[i].size <= 10; - } + options.fp16_rtz = !util_format_is_pure_integer(info->dst.format) && + dst_desc->channel[i].size <= 10; struct hash_entry *entry = _mesa_hash_table_search(sctx->cs_blit_shaders, (void*)(uintptr_t)options.key); -- 2.7.4