From 262ca98b3a45075800d88abb9a069d8c21578330 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Thu, 24 Sep 2020 11:31:13 -0700 Subject: [PATCH] intel/compiler: Remove Gen10-specific code Reviewed-by: Jason Ekstrand Part-of: --- src/intel/compiler/brw_fs_generator.cpp | 17 +---------------- src/intel/compiler/brw_gen_enum.h | 1 - src/intel/compiler/brw_shader.cpp | 7 ------- src/intel/compiler/brw_vec4.cpp | 6 ------ src/intel/compiler/brw_vec4_gs_visitor.cpp | 6 ------ src/intel/compiler/brw_vec4_tcs.cpp | 7 ------- src/intel/compiler/test_eu_compact.cpp | 5 ++++- src/intel/compiler/test_eu_validate.cpp | 5 ++--- 8 files changed, 7 insertions(+), 47 deletions(-) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 9e96ca9..1ad82aa 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -837,22 +837,7 @@ fs_generator::generate_urb_read(fs_inst *inst, void fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload) { - brw_inst *insn; - - /* WaClearTDRRegBeforeEOTForNonPS. - * - * WA: Clear tdr register before send EOT in all non-PS shader kernels - * - * mov(8) tdr0:ud 0x0:ud {NoMask}" - */ - if (inst->eot && p->devinfo->gen == 10) { - brw_push_insn_state(p); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_MOV(p, brw_tdr_reg(), brw_imm_uw(0)); - brw_pop_insn_state(p); - } - - insn = brw_next_insn(p, BRW_OPCODE_SEND); + brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND); brw_set_dest(p, insn, brw_null_reg()); brw_set_src0(p, insn, payload); diff --git a/src/intel/compiler/brw_gen_enum.h b/src/intel/compiler/brw_gen_enum.h index cd50f9c..1746600 100644 --- a/src/intel/compiler/brw_gen_enum.h +++ b/src/intel/compiler/brw_gen_enum.h @@ -53,7 +53,6 @@ gen_from_devinfo(const struct gen_device_info *devinfo) case 7: return devinfo->is_haswell ? GEN75 : GEN7; case 8: return GEN8; case 9: return GEN9; - case 10: return GEN10; case 11: return GEN11; case 12: return GEN12; default: diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 2ea680d..d137c7d 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -1299,13 +1299,6 @@ brw_compile_tes(const struct brw_compiler *compiler, /* URB entry sizes are stored as a multiple of 64 bytes. */ prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64; - /* On Cannonlake software shall not program an allocation size that - * specifies a size that is a multiple of 3 64B (512-bit) cachelines. - */ - if (devinfo->gen == 10 && - prog_data->base.urb_entry_size % 3 == 0) - prog_data->base.urb_entry_size++; - prog_data->base.urb_read_length = 0; STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1); diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index 02980b8..8b97312 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -2937,12 +2937,6 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, prog_data->base.urb_entry_size = DIV_ROUND_UP(vue_entries, 8); } else { prog_data->base.urb_entry_size = DIV_ROUND_UP(vue_entries, 4); - /* On Cannonlake software shall not program an allocation size that - * specifies a size that is a multiple of 3 64B (512-bit) cachelines. - */ - if (compiler->devinfo->gen == 10 && - prog_data->base.urb_entry_size % 3 == 0) - prog_data->base.urb_entry_size++; } if (INTEL_DEBUG & DEBUG_VS) { diff --git a/src/intel/compiler/brw_vec4_gs_visitor.cpp b/src/intel/compiler/brw_vec4_gs_visitor.cpp index 4800d9b..3e0aba0 100644 --- a/src/intel/compiler/brw_vec4_gs_visitor.cpp +++ b/src/intel/compiler/brw_vec4_gs_visitor.cpp @@ -790,12 +790,6 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data, */ if (compiler->devinfo->gen >= 7) { prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64; - /* On Cannonlake software shall not program an allocation size that - * specifies a size that is a multiple of 3 64B (512-bit) cachelines. - */ - if (compiler->devinfo->gen == 10 && - prog_data->base.urb_entry_size % 3 == 0) - prog_data->base.urb_entry_size++; } else { prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 128) / 128; } diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp index 1009e3b..2a4c379 100644 --- a/src/intel/compiler/brw_vec4_tcs.cpp +++ b/src/intel/compiler/brw_vec4_tcs.cpp @@ -440,13 +440,6 @@ brw_compile_tcs(const struct brw_compiler *compiler, /* URB entry sizes are stored as a multiple of 64 bytes. */ vue_prog_data->urb_entry_size = ALIGN(output_size_bytes, 64) / 64; - /* On Cannonlake software shall not program an allocation size that - * specifies a size that is a multiple of 3 64B (512-bit) cachelines. - */ - if (devinfo->gen == 10 && - vue_prog_data->urb_entry_size % 3 == 0) - vue_prog_data->urb_entry_size++; - /* HS does not use the usual payload pushing from URB to GRFs, * because we don't have enough registers for a full-size payload, and * the hardware is broken on Haswell anyway. diff --git a/src/intel/compiler/test_eu_compact.cpp b/src/intel/compiler/test_eu_compact.cpp index 74f7aae..a371a32 100644 --- a/src/intel/compiler/test_eu_compact.cpp +++ b/src/intel/compiler/test_eu_compact.cpp @@ -328,12 +328,15 @@ run_tests(const struct gen_device_info *devinfo) } int -main(int argc, char **argv) +main(UNUSED int argc, UNUSED char **argv) { struct gen_device_info *devinfo = (struct gen_device_info *)calloc(1, sizeof(*devinfo)); bool fail = false; for (devinfo->gen = 5; devinfo->gen <= 12; devinfo->gen++) { + if (devinfo->gen == 10) + continue; + fail |= run_tests(devinfo); } diff --git a/src/intel/compiler/test_eu_validate.cpp b/src/intel/compiler/test_eu_validate.cpp index a270519..185ceb9 100644 --- a/src/intel/compiler/test_eu_validate.cpp +++ b/src/intel/compiler/test_eu_validate.cpp @@ -46,7 +46,6 @@ static const struct gen_info { { "glk", }, { "cfl", }, { "whl", }, - { "cnl", }, { "icl", }, { "tgl", }, }; @@ -485,8 +484,8 @@ TEST_P(validation_test, invalid_type_encoding_3src_a1) /* There are no ternary instructions that can operate on B-type sources * on Gen11-12. Src1/Src2 cannot be B-typed either. */ - { BRW_REGISTER_TYPE_B, E(INT), devinfo.gen == 10 }, - { BRW_REGISTER_TYPE_UB, E(INT), devinfo.gen == 10 }, + { BRW_REGISTER_TYPE_B, E(INT), false }, + { BRW_REGISTER_TYPE_UB, E(INT), false }, }; /* Initially assume all hardware encodings are invalid */ -- 2.7.4