From 262a72f50f1887591558ce0f521a5f7d3a17e2c2 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 26 Apr 2021 15:29:34 -0700 Subject: [PATCH] [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. Reduces the amount of vector ALU operations and reduces vector register pressure. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 62 ++-- .../RISCV/rvv/fixed-vectors-reduction-int.ll | 240 ++++++++-------- llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll | 320 ++++++++++----------- llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll | 64 ++--- llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll | 64 ++--- llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll | 144 +++++----- llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll | 164 +++++------ llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll | 64 ++--- llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll | 64 ++--- llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll | 64 ++--- llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll | 64 ++--- llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll | 64 ++--- llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll | 64 ++--- .../test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll | 105 +++---- llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll | 144 +++++----- llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll | 164 +++++------ llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll | 64 ++--- llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll | 64 ++--- llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll | 64 ++--- llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll | 90 +++--- llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll | 64 ++--- llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll | 64 ++--- llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll | 64 ++--- llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll | 64 ++--- 24 files changed, 1215 insertions(+), 1178 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index fd4e455..bd130df 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -1511,18 +1511,15 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, return SDValue(); } -// Called by type legalization to handle splat of i64 on RV32. -// FIXME: We can optimize this when the type has sign or zero bits in one -// of the halves. -static SDValue splatSplitI64WithVL(const SDLoc &DL, MVT VT, SDValue Scalar, - SDValue VL, SelectionDAG &DAG, - const RISCVSubtarget &Subtarget) { - SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Scalar, - DAG.getConstant(0, DL, MVT::i32)); - SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Scalar, - DAG.getConstant(1, DL, MVT::i32)); - - // Fall back to a stack store and stride x0 vector load. +// Use a stack slot to splat the two i32 values in Lo/Hi to the vector desired +// vector nxvXi64 VT. +static SDValue splatPartsI64ThroughStack(const SDLoc &DL, MVT VT, SDValue Lo, + SDValue Hi, SDValue VL, + SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) { + assert(VT.getVectorElementType() == MVT::i64 && VT.isScalableVector() && + Lo.getValueType() == MVT::i32 && Hi.getValueType() == MVT::i32 && + "Unexpected VTs!"); MachineFunction &MF = DAG.getMachineFunction(); RISCVMachineFunctionInfo *FuncInfo = MF.getInfo(); @@ -1553,6 +1550,21 @@ static SDValue splatSplitI64WithVL(const SDLoc &DL, MVT VT, SDValue Scalar, MPI, Align(8), MachineMemOperand::MOLoad); } +// Called by type legalization to handle splat of i64 on RV32. +// FIXME: We can optimize this when the type has sign or zero bits in one +// of the halves. +static SDValue splatSplitI64WithVL(const SDLoc &DL, MVT VT, SDValue Scalar, + SDValue VL, SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) { + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Scalar, + DAG.getConstant(0, DL, MVT::i32)); + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Scalar, + DAG.getConstant(1, DL, MVT::i32)); + + // Fall back to a stack store and stride x0 vector load. + return splatPartsI64ThroughStack(DL, VT, Lo, Hi, VL, DAG, Subtarget); +} + // This function lowers a splat of a scalar operand Splat with the vector // length VL. It ensures the final sequence is type legal, which is useful when // lowering a splat after type legalization. @@ -2761,7 +2773,7 @@ SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, SDValue RISCVTargetLowering::lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); - EVT VecVT = Op.getValueType(); + MVT VecVT = Op.getSimpleValueType(); assert(!Subtarget.is64Bit() && VecVT.getVectorElementType() == MVT::i64 && "Unexpected SPLAT_VECTOR_PARTS lowering"); @@ -2784,27 +2796,9 @@ SDValue RISCVTargetLowering::lowerSPLAT_VECTOR_PARTS(SDValue Op, Hi.getConstantOperandVal(1) == 31) return DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, Lo); - // Else, on RV32 we lower an i64-element SPLAT_VECTOR thus, being careful not - // to accidentally sign-extend the 32-bit halves to the e64 SEW: - // vmv.v.x vX, hi - // vsll.vx vX, vX, /*32*/ - // vmv.v.x vY, lo - // vsll.vx vY, vY, /*32*/ - // vsrl.vx vY, vY, /*32*/ - // vor.vv vX, vX, vY - SDValue ThirtyTwoV = DAG.getConstant(32, DL, VecVT); - - Lo = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, Lo); - Lo = DAG.getNode(ISD::SHL, DL, VecVT, Lo, ThirtyTwoV); - Lo = DAG.getNode(ISD::SRL, DL, VecVT, Lo, ThirtyTwoV); - - if (isNullConstant(Hi)) - return Lo; - - Hi = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, Hi); - Hi = DAG.getNode(ISD::SHL, DL, VecVT, Hi, ThirtyTwoV); - - return DAG.getNode(ISD::OR, DL, VecVT, Lo, Hi); + // Fall back to use a stack store and stride x0 vector load. Use X0 as VL. + return splatPartsI64ThroughStack( + DL, VecVT, Lo, Hi, DAG.getRegister(RISCV::X0, MVT::i64), DAG, Subtarget); } // Custom-lower extensions from mask vectors by using a vselect either with 1 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll index d6bde2d..c9b5b28 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll @@ -3527,24 +3527,26 @@ declare i64 @llvm.vector.reduce.smin.v2i64(<2 x i64>) define i64 @vreduce_smin_v2i64(<2 x i64>* %x) { ; RV32-LABEL: vreduce_smin_v2i64: ; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu ; RV32-NEXT: vle64.v v25, (a0) -; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; RV32-NEXT: vmv.v.i v26, -1 -; RV32-NEXT: addi a1, zero, 32 -; RV32-NEXT: vsll.vx v26, v26, a1 -; RV32-NEXT: vsrl.vx v26, v26, a1 +; RV32-NEXT: addi a0, zero, -1 +; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: addi a0, a0, -1 -; RV32-NEXT: vmv.v.x v27, a0 -; RV32-NEXT: vsll.vx v27, v27, a1 -; RV32-NEXT: vor.vv v26, v26, v27 +; RV32-NEXT: sw a0, 12(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v26, (a0), zero ; RV32-NEXT: vsetivli a0, 2, e64,m1,ta,mu ; RV32-NEXT: vredmin.vs v25, v25, v26 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v2i64: @@ -3569,25 +3571,27 @@ declare i64 @llvm.vector.reduce.smin.v4i64(<4 x i64>) define i64 @vreduce_smin_v4i64(<4 x i64>* %x) { ; RV32-LABEL: vreduce_smin_v4i64: ; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli a1, 4, e64,m2,ta,mu ; RV32-NEXT: vle64.v v26, (a0) -; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; RV32-NEXT: vmv.v.i v25, -1 -; RV32-NEXT: addi a1, zero, 32 -; RV32-NEXT: vsll.vx v25, v25, a1 -; RV32-NEXT: vsrl.vx v25, v25, a1 +; RV32-NEXT: addi a0, zero, -1 +; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: addi a0, a0, -1 -; RV32-NEXT: vmv.v.x v28, a0 -; RV32-NEXT: vsll.vx v28, v28, a1 -; RV32-NEXT: vor.vv v25, v25, v28 +; RV32-NEXT: sw a0, 12(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero ; RV32-NEXT: vsetivli a0, 4, e64,m2,ta,mu ; RV32-NEXT: vredmin.vs v25, v26, v25 ; RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v4i64: @@ -3613,25 +3617,27 @@ declare i64 @llvm.vector.reduce.smin.v8i64(<8 x i64>) define i64 @vreduce_smin_v8i64(<8 x i64>* %x) { ; RV32-LABEL: vreduce_smin_v8i64: ; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli a1, 8, e64,m4,ta,mu ; RV32-NEXT: vle64.v v28, (a0) -; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; RV32-NEXT: vmv.v.i v25, -1 -; RV32-NEXT: addi a1, zero, 32 -; RV32-NEXT: vsll.vx v25, v25, a1 -; RV32-NEXT: vsrl.vx v25, v25, a1 +; RV32-NEXT: addi a0, zero, -1 +; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: addi a0, a0, -1 -; RV32-NEXT: vmv.v.x v26, a0 -; RV32-NEXT: vsll.vx v26, v26, a1 -; RV32-NEXT: vor.vv v25, v25, v26 +; RV32-NEXT: sw a0, 12(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero ; RV32-NEXT: vsetivli a0, 8, e64,m4,ta,mu ; RV32-NEXT: vredmin.vs v25, v28, v25 ; RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v8i64: @@ -3657,25 +3663,27 @@ declare i64 @llvm.vector.reduce.smin.v16i64(<16 x i64>) define i64 @vreduce_smin_v16i64(<16 x i64>* %x) { ; RV32-LABEL: vreduce_smin_v16i64: ; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli a1, 16, e64,m8,ta,mu ; RV32-NEXT: vle64.v v8, (a0) -; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; RV32-NEXT: vmv.v.i v25, -1 -; RV32-NEXT: addi a1, zero, 32 -; RV32-NEXT: vsll.vx v25, v25, a1 -; RV32-NEXT: vsrl.vx v25, v25, a1 +; RV32-NEXT: addi a0, zero, -1 +; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: addi a0, a0, -1 -; RV32-NEXT: vmv.v.x v26, a0 -; RV32-NEXT: vsll.vx v26, v26, a1 -; RV32-NEXT: vor.vv v25, v25, v26 +; RV32-NEXT: sw a0, 12(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero ; RV32-NEXT: vsetivli a0, 16, e64,m8,ta,mu ; RV32-NEXT: vredmin.vs v25, v8, v25 ; RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v16i64: @@ -3701,28 +3709,30 @@ declare i64 @llvm.vector.reduce.smin.v32i64(<32 x i64>) define i64 @vreduce_smin_v32i64(<32 x i64>* %x) { ; RV32-LABEL: vreduce_smin_v32i64: ; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli a1, 16, e64,m8,ta,mu ; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a0, a0, 128 ; RV32-NEXT: vle64.v v16, (a0) -; RV32-NEXT: vmin.vv v8, v8, v16 -; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; RV32-NEXT: vmv.v.i v25, -1 -; RV32-NEXT: addi a1, zero, 32 -; RV32-NEXT: vsll.vx v25, v25, a1 -; RV32-NEXT: vsrl.vx v25, v25, a1 +; RV32-NEXT: addi a0, zero, -1 +; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: addi a0, a0, -1 -; RV32-NEXT: vmv.v.x v26, a0 -; RV32-NEXT: vsll.vx v26, v26, a1 -; RV32-NEXT: vor.vv v25, v25, v26 +; RV32-NEXT: sw a0, 12(sp) +; RV32-NEXT: vmin.vv v8, v8, v16 +; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero ; RV32-NEXT: vsetivli a0, 16, e64,m8,ta,mu ; RV32-NEXT: vredmin.vs v25, v8, v25 ; RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v32i64: @@ -3751,34 +3761,35 @@ declare i64 @llvm.vector.reduce.smin.v64i64(<64 x i64>) define i64 @vreduce_smin_v64i64(<64 x i64>* %x) nounwind { ; RV32-LABEL: vreduce_smin_v64i64: ; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: vsetivli a1, 16, e64,m8,ta,mu ; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a1, a0, 256 -; RV32-NEXT: addi a2, a0, 384 -; RV32-NEXT: vle64.v v16, (a2) +; RV32-NEXT: vle64.v v16, (a1) +; RV32-NEXT: addi a1, a0, 384 +; RV32-NEXT: vle64.v v24, (a1) ; RV32-NEXT: addi a0, a0, 128 -; RV32-NEXT: vle64.v v24, (a0) -; RV32-NEXT: vle64.v v0, (a1) -; RV32-NEXT: vmin.vv v16, v24, v16 -; RV32-NEXT: vmin.vv v8, v8, v0 -; RV32-NEXT: vmin.vv v8, v8, v16 -; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; RV32-NEXT: vmv.v.i v25, -1 -; RV32-NEXT: addi a1, zero, 32 -; RV32-NEXT: vsll.vx v25, v25, a1 -; RV32-NEXT: vsrl.vx v25, v25, a1 +; RV32-NEXT: vle64.v v0, (a0) +; RV32-NEXT: addi a0, zero, -1 +; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: addi a0, a0, -1 -; RV32-NEXT: vmv.v.x v26, a0 -; RV32-NEXT: vsll.vx v26, v26, a1 -; RV32-NEXT: vor.vv v25, v25, v26 +; RV32-NEXT: sw a0, 12(sp) +; RV32-NEXT: vmin.vv v24, v0, v24 +; RV32-NEXT: vmin.vv v8, v8, v16 +; RV32-NEXT: vmin.vv v8, v8, v24 +; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero ; RV32-NEXT: vsetivli a0, 16, e64,m8,ta,mu ; RV32-NEXT: vredmin.vs v25, v8, v25 ; RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v64i64: @@ -4308,23 +4319,24 @@ declare i64 @llvm.vector.reduce.smax.v2i64(<2 x i64>) define i64 @vreduce_smax_v2i64(<2 x i64>* %x) { ; RV32-LABEL: vreduce_smax_v2i64: ; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu ; RV32-NEXT: vle64.v v25, (a0) ; RV32-NEXT: lui a0, 524288 -; RV32-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; RV32-NEXT: vmv.v.x v26, a0 -; RV32-NEXT: addi a1, zero, 32 -; RV32-NEXT: vsll.vx v26, v26, a1 -; RV32-NEXT: vmv.v.i v27, 0 -; RV32-NEXT: vsll.vx v27, v27, a1 -; RV32-NEXT: vsrl.vx v27, v27, a1 -; RV32-NEXT: vor.vv v26, v27, v26 +; RV32-NEXT: sw a0, 12(sp) +; RV32-NEXT: sw zero, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v26, (a0), zero ; RV32-NEXT: vsetivli a0, 2, e64,m1,ta,mu ; RV32-NEXT: vredmax.vs v25, v25, v26 ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smax_v2i64: @@ -4349,24 +4361,25 @@ declare i64 @llvm.vector.reduce.smax.v4i64(<4 x i64>) define i64 @vreduce_smax_v4i64(<4 x i64>* %x) { ; RV32-LABEL: vreduce_smax_v4i64: ; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli a1, 4, e64,m2,ta,mu ; RV32-NEXT: vle64.v v26, (a0) ; RV32-NEXT: lui a0, 524288 -; RV32-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; RV32-NEXT: vmv.v.x v25, a0 -; RV32-NEXT: addi a1, zero, 32 -; RV32-NEXT: vsll.vx v25, v25, a1 -; RV32-NEXT: vmv.v.i v28, 0 -; RV32-NEXT: vsll.vx v28, v28, a1 -; RV32-NEXT: vsrl.vx v28, v28, a1 -; RV32-NEXT: vor.vv v25, v28, v25 +; RV32-NEXT: sw a0, 12(sp) +; RV32-NEXT: sw zero, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero ; RV32-NEXT: vsetivli a0, 4, e64,m2,ta,mu ; RV32-NEXT: vredmax.vs v25, v26, v25 ; RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smax_v4i64: @@ -4392,24 +4405,25 @@ declare i64 @llvm.vector.reduce.smax.v8i64(<8 x i64>) define i64 @vreduce_smax_v8i64(<8 x i64>* %x) { ; RV32-LABEL: vreduce_smax_v8i64: ; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli a1, 8, e64,m4,ta,mu ; RV32-NEXT: vle64.v v28, (a0) ; RV32-NEXT: lui a0, 524288 -; RV32-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; RV32-NEXT: vmv.v.x v25, a0 -; RV32-NEXT: addi a1, zero, 32 -; RV32-NEXT: vsll.vx v25, v25, a1 -; RV32-NEXT: vmv.v.i v26, 0 -; RV32-NEXT: vsll.vx v26, v26, a1 -; RV32-NEXT: vsrl.vx v26, v26, a1 -; RV32-NEXT: vor.vv v25, v26, v25 +; RV32-NEXT: sw a0, 12(sp) +; RV32-NEXT: sw zero, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero ; RV32-NEXT: vsetivli a0, 8, e64,m4,ta,mu ; RV32-NEXT: vredmax.vs v25, v28, v25 ; RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smax_v8i64: @@ -4435,24 +4449,25 @@ declare i64 @llvm.vector.reduce.smax.v16i64(<16 x i64>) define i64 @vreduce_smax_v16i64(<16 x i64>* %x) { ; RV32-LABEL: vreduce_smax_v16i64: ; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli a1, 16, e64,m8,ta,mu ; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: lui a0, 524288 -; RV32-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; RV32-NEXT: vmv.v.x v25, a0 -; RV32-NEXT: addi a1, zero, 32 -; RV32-NEXT: vsll.vx v25, v25, a1 -; RV32-NEXT: vmv.v.i v26, 0 -; RV32-NEXT: vsll.vx v26, v26, a1 -; RV32-NEXT: vsrl.vx v26, v26, a1 -; RV32-NEXT: vor.vv v25, v26, v25 +; RV32-NEXT: sw a0, 12(sp) +; RV32-NEXT: sw zero, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero ; RV32-NEXT: vsetivli a0, 16, e64,m8,ta,mu ; RV32-NEXT: vredmax.vs v25, v8, v25 ; RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smax_v16i64: @@ -4478,27 +4493,28 @@ declare i64 @llvm.vector.reduce.smax.v32i64(<32 x i64>) define i64 @vreduce_smax_v32i64(<32 x i64>* %x) { ; RV32-LABEL: vreduce_smax_v32i64: ; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli a1, 16, e64,m8,ta,mu ; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a0, a0, 128 ; RV32-NEXT: vle64.v v16, (a0) -; RV32-NEXT: vmax.vv v8, v8, v16 ; RV32-NEXT: lui a0, 524288 -; RV32-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; RV32-NEXT: vmv.v.x v25, a0 -; RV32-NEXT: addi a1, zero, 32 -; RV32-NEXT: vsll.vx v25, v25, a1 -; RV32-NEXT: vmv.v.i v26, 0 -; RV32-NEXT: vsll.vx v26, v26, a1 -; RV32-NEXT: vsrl.vx v26, v26, a1 -; RV32-NEXT: vor.vv v25, v26, v25 +; RV32-NEXT: sw a0, 12(sp) +; RV32-NEXT: sw zero, 8(sp) +; RV32-NEXT: vmax.vv v8, v8, v16 +; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero ; RV32-NEXT: vsetivli a0, 16, e64,m8,ta,mu ; RV32-NEXT: vredmax.vs v25, v8, v25 ; RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smax_v32i64: @@ -4527,33 +4543,33 @@ declare i64 @llvm.vector.reduce.smax.v64i64(<64 x i64>) define i64 @vreduce_smax_v64i64(<64 x i64>* %x) nounwind { ; RV32-LABEL: vreduce_smax_v64i64: ; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: vsetivli a1, 16, e64,m8,ta,mu ; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a1, a0, 256 -; RV32-NEXT: addi a2, a0, 384 -; RV32-NEXT: vle64.v v16, (a2) +; RV32-NEXT: vle64.v v16, (a1) +; RV32-NEXT: addi a1, a0, 384 +; RV32-NEXT: vle64.v v24, (a1) ; RV32-NEXT: addi a0, a0, 128 -; RV32-NEXT: vle64.v v24, (a0) -; RV32-NEXT: vle64.v v0, (a1) -; RV32-NEXT: vmax.vv v16, v24, v16 -; RV32-NEXT: vmax.vv v8, v8, v0 -; RV32-NEXT: vmax.vv v8, v8, v16 +; RV32-NEXT: vle64.v v0, (a0) ; RV32-NEXT: lui a0, 524288 -; RV32-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; RV32-NEXT: vmv.v.x v25, a0 -; RV32-NEXT: addi a1, zero, 32 -; RV32-NEXT: vsll.vx v25, v25, a1 -; RV32-NEXT: vmv.v.i v26, 0 -; RV32-NEXT: vsll.vx v26, v26, a1 -; RV32-NEXT: vsrl.vx v26, v26, a1 -; RV32-NEXT: vor.vv v25, v26, v25 +; RV32-NEXT: sw a0, 12(sp) +; RV32-NEXT: sw zero, 8(sp) +; RV32-NEXT: vmax.vv v24, v0, v24 +; RV32-NEXT: vmax.vv v8, v8, v16 +; RV32-NEXT: vmax.vv v8, v8, v24 +; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero ; RV32-NEXT: vsetivli a0, 16, e64,m8,ta,mu ; RV32-NEXT: vredmax.vs v25, v8, v25 ; RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu ; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; RV32-NEXT: vsrl.vx v25, v25, a1 ; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smax_v64i64: diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll index 6125197..eec8484 100644 --- a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll @@ -2226,15 +2226,15 @@ define @icmp_eq_vv_nxv8i64( %va, @icmp_eq_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_eq_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmseq.vv v0, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2245,15 +2245,15 @@ define @icmp_eq_vx_nxv8i64( %va, i64 %b) { define @icmp_eq_xv_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_eq_xv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmseq.vv v0, v16, v8 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2310,15 +2310,15 @@ define @icmp_ne_vv_nxv8i64( %va, @icmp_ne_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_ne_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmsne.vv v0, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2329,15 +2329,15 @@ define @icmp_ne_vx_nxv8i64( %va, i64 %b) { define @icmp_ne_xv_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_ne_xv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmsne.vv v0, v16, v8 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2370,15 +2370,15 @@ define @icmp_ugt_vv_nxv8i64( %va, @icmp_ugt_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_ugt_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmsltu.vv v0, v16, v8 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2389,15 +2389,15 @@ define @icmp_ugt_vx_nxv8i64( %va, i64 %b) { define @icmp_ugt_xv_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_ugt_xv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmsltu.vv v0, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2430,15 +2430,15 @@ define @icmp_uge_vv_nxv8i64( %va, @icmp_uge_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_uge_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmsleu.vv v0, v16, v8 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2449,15 +2449,15 @@ define @icmp_uge_vx_nxv8i64( %va, i64 %b) { define @icmp_uge_xv_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_uge_xv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2563,15 +2563,15 @@ define @icmp_ult_vv_nxv8i64( %va, @icmp_ult_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_ult_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmsltu.vv v0, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2582,15 +2582,15 @@ define @icmp_ult_vx_nxv8i64( %va, i64 %b) { define @icmp_ult_xv_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_ult_xv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmsltu.vv v0, v16, v8 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2684,15 +2684,15 @@ define @icmp_ule_vv_nxv8i64( %va, @icmp_ule_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_ule_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2703,15 +2703,15 @@ define @icmp_ule_vx_nxv8i64( %va, i64 %b) { define @icmp_ule_xv_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_ule_xv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmsleu.vv v0, v16, v8 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2744,15 +2744,15 @@ define @icmp_sgt_vv_nxv8i64( %va, @icmp_sgt_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_sgt_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmslt.vv v0, v16, v8 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2763,15 +2763,15 @@ define @icmp_sgt_vx_nxv8i64( %va, i64 %b) { define @icmp_sgt_xv_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_sgt_xv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmslt.vv v0, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2804,15 +2804,15 @@ define @icmp_sge_vv_nxv8i64( %va, @icmp_sge_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_sge_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmsle.vv v0, v16, v8 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2823,15 +2823,15 @@ define @icmp_sge_vx_nxv8i64( %va, i64 %b) { define @icmp_sge_xv_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_sge_xv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmsle.vv v0, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2913,15 +2913,15 @@ define @icmp_slt_vv_nxv8i64( %va, @icmp_slt_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_slt_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmslt.vv v0, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2932,15 +2932,15 @@ define @icmp_slt_vx_nxv8i64( %va, i64 %b) { define @icmp_slt_xv_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_slt_xv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmslt.vv v0, v16, v8 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -3022,15 +3022,15 @@ define @icmp_sle_vv_nxv8i64( %va, @icmp_sle_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_sle_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmsle.vv v0, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -3041,15 +3041,15 @@ define @icmp_sle_vx_nxv8i64( %va, i64 %b) { define @icmp_sle_xv_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: icmp_sle_xv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmsle.vv v0, v16, v8 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll index 84f1190..063fd62 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll @@ -667,15 +667,15 @@ define @vadd_vx_nxv16i32_1( %va) { define @vadd_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vadd_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vadd.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -710,15 +710,15 @@ define @vadd_vx_nxv1i64_1( %va) { define @vadd_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vadd_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vadd.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -753,15 +753,15 @@ define @vadd_vx_nxv2i64_1( %va) { define @vadd_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vadd_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vadd.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -796,15 +796,15 @@ define @vadd_vx_nxv4i64_1( %va) { define @vadd_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vadd_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vadd.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll index 54f909c..48e32dd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll @@ -1076,15 +1076,15 @@ define @vand_vv_nxv1i64( %va, @vand_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vand_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vand.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1142,15 +1142,15 @@ define @vand_vv_nxv2i64( %va, @vand_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vand_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vand.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1208,15 +1208,15 @@ define @vand_vv_nxv4i64( %va, @vand_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vand_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vand.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1274,15 +1274,15 @@ define @vand_vv_nxv8i64( %va, @vand_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vand_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vand.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll index 3216789..edf741e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll @@ -752,15 +752,15 @@ define @vdiv_vv_nxv1i64( %va, @vdiv_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vdiv_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vdiv.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -771,23 +771,23 @@ define @vdiv_vx_nxv1i64( %va, i64 %b) { define @vdiv_vi_nxv1i64_0( %va) { ; CHECK-LABEL: vdiv_vi_nxv1i64_0: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: lui a0, 748983 ; CHECK-NEXT: addi a0, a0, -586 -; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: addi a0, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a0 -; CHECK-NEXT: lui a1, 898779 -; CHECK-NEXT: addi a1, a1, 1755 -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: vsll.vx v26, v26, a0 -; CHECK-NEXT: vsrl.vx v26, v26, a0 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: lui a0, 898779 +; CHECK-NEXT: addi a0, a0, 1755 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vmulh.vv v25, v8, v25 ; CHECK-NEXT: addi a0, zero, 63 ; CHECK-NEXT: vsrl.vx v26, v25, a0 ; CHECK-NEXT: vsra.vi v25, v25, 1 ; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -808,15 +808,15 @@ define @vdiv_vv_nxv2i64( %va, @vdiv_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vdiv_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vdiv.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -827,23 +827,23 @@ define @vdiv_vx_nxv2i64( %va, i64 %b) { define @vdiv_vi_nxv2i64_0( %va) { ; CHECK-LABEL: vdiv_vi_nxv2i64_0: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: lui a0, 748983 ; CHECK-NEXT: addi a0, a0, -586 -; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: addi a0, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a0 -; CHECK-NEXT: lui a1, 898779 -; CHECK-NEXT: addi a1, a1, 1755 -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: vsll.vx v28, v28, a0 -; CHECK-NEXT: vsrl.vx v28, v28, a0 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: lui a0, 898779 +; CHECK-NEXT: addi a0, a0, 1755 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vmulh.vv v26, v8, v26 ; CHECK-NEXT: addi a0, zero, 63 ; CHECK-NEXT: vsrl.vx v28, v26, a0 ; CHECK-NEXT: vsra.vi v26, v26, 1 ; CHECK-NEXT: vadd.vv v8, v26, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -864,15 +864,15 @@ define @vdiv_vv_nxv4i64( %va, @vdiv_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vdiv_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vdiv.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -883,23 +883,23 @@ define @vdiv_vx_nxv4i64( %va, i64 %b) { define @vdiv_vi_nxv4i64_0( %va) { ; CHECK-LABEL: vdiv_vi_nxv4i64_0: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: lui a0, 748983 ; CHECK-NEXT: addi a0, a0, -586 -; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: addi a0, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a0 -; CHECK-NEXT: lui a1, 898779 -; CHECK-NEXT: addi a1, a1, 1755 -; CHECK-NEXT: vmv.v.x v12, a1 -; CHECK-NEXT: vsll.vx v12, v12, a0 -; CHECK-NEXT: vsrl.vx v12, v12, a0 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: lui a0, 898779 +; CHECK-NEXT: addi a0, a0, 1755 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vmulh.vv v28, v8, v28 ; CHECK-NEXT: addi a0, zero, 63 ; CHECK-NEXT: vsrl.vx v8, v28, a0 ; CHECK-NEXT: vsra.vi v28, v28, 1 ; CHECK-NEXT: vadd.vv v8, v28, v8 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -920,15 +920,15 @@ define @vdiv_vv_nxv8i64( %va, @vdiv_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vdiv_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vdiv.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -939,23 +939,23 @@ define @vdiv_vx_nxv8i64( %va, i64 %b) { define @vdiv_vi_nxv8i64_0( %va) { ; CHECK-LABEL: vdiv_vi_nxv8i64_0: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: lui a0, 748983 ; CHECK-NEXT: addi a0, a0, -586 -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a0 -; CHECK-NEXT: addi a0, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a0 -; CHECK-NEXT: lui a1, 898779 -; CHECK-NEXT: addi a1, a1, 1755 -; CHECK-NEXT: vmv.v.x v24, a1 -; CHECK-NEXT: vsll.vx v24, v24, a0 -; CHECK-NEXT: vsrl.vx v24, v24, a0 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: lui a0, 898779 +; CHECK-NEXT: addi a0, a0, 1755 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmulh.vv v8, v8, v16 ; CHECK-NEXT: addi a0, zero, 63 ; CHECK-NEXT: vsrl.vx v16, v8, a0 ; CHECK-NEXT: vsra.vi v8, v8, 1 ; CHECK-NEXT: vadd.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll index 383d3f3..4ec41a6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll @@ -751,15 +751,15 @@ define @vdivu_vv_nxv1i64( %va, @vdivu_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vdivu_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vdivu.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -770,21 +770,22 @@ define @vdivu_vx_nxv1i64( %va, i64 %b) { define @vdivu_vi_nxv1i64_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv1i64_0: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.i v25, -7 ; CHECK-NEXT: lui a0, 131072 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: addi a0, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a0 -; CHECK-NEXT: vmv.v.i v27, 1 -; CHECK-NEXT: vsll.vx v27, v27, a0 -; CHECK-NEXT: vsrl.vx v27, v27, a0 -; CHECK-NEXT: vor.vv v26, v27, v26 -; CHECK-NEXT: vmulhu.vv v26, v8, v26 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: addi a0, zero, 1 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero +; CHECK-NEXT: vmv.v.i v26, -7 +; CHECK-NEXT: vmulhu.vv v25, v8, v25 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v26, v26, a0 -; CHECK-NEXT: vmseq.vi v0, v25, 1 -; CHECK-NEXT: vmerge.vvm v8, v26, v8, v0 +; CHECK-NEXT: vsrl.vx v25, v25, a0 +; CHECK-NEXT: vmseq.vi v0, v26, 1 +; CHECK-NEXT: vmerge.vvm v8, v25, v8, v0 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -805,15 +806,15 @@ define @vdivu_vv_nxv2i64( %va, @vdivu_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vdivu_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vdivu.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -824,21 +825,22 @@ define @vdivu_vx_nxv2i64( %va, i64 %b) { define @vdivu_vi_nxv2i64_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv2i64_0: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.i v26, -7 ; CHECK-NEXT: lui a0, 131072 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: addi a0, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a0 -; CHECK-NEXT: vmv.v.i v30, 1 -; CHECK-NEXT: vsll.vx v30, v30, a0 -; CHECK-NEXT: vsrl.vx v30, v30, a0 -; CHECK-NEXT: vor.vv v28, v30, v28 -; CHECK-NEXT: vmulhu.vv v28, v8, v28 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: addi a0, zero, 1 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero +; CHECK-NEXT: vmv.v.i v28, -7 +; CHECK-NEXT: vmulhu.vv v26, v8, v26 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v28, v28, a0 -; CHECK-NEXT: vmseq.vi v0, v26, 1 -; CHECK-NEXT: vmerge.vvm v8, v28, v8, v0 +; CHECK-NEXT: vsrl.vx v26, v26, a0 +; CHECK-NEXT: vmseq.vi v0, v28, 1 +; CHECK-NEXT: vmerge.vvm v8, v26, v8, v0 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -859,15 +861,15 @@ define @vdivu_vv_nxv4i64( %va, @vdivu_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vdivu_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vdivu.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -878,21 +880,22 @@ define @vdivu_vx_nxv4i64( %va, i64 %b) { define @vdivu_vi_nxv4i64_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv4i64_0: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.i v28, -7 ; CHECK-NEXT: lui a0, 131072 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: addi a0, zero, 32 -; CHECK-NEXT: vsll.vx v12, v12, a0 -; CHECK-NEXT: vmv.v.i v16, 1 -; CHECK-NEXT: vsll.vx v16, v16, a0 -; CHECK-NEXT: vsrl.vx v16, v16, a0 -; CHECK-NEXT: vor.vv v12, v16, v12 -; CHECK-NEXT: vmulhu.vv v12, v8, v12 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: addi a0, zero, 1 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero +; CHECK-NEXT: vmv.v.i v12, -7 +; CHECK-NEXT: vmulhu.vv v28, v8, v28 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v12, v12, a0 -; CHECK-NEXT: vmseq.vi v0, v28, 1 -; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 +; CHECK-NEXT: vsrl.vx v28, v28, a0 +; CHECK-NEXT: vmseq.vi v0, v12, 1 +; CHECK-NEXT: vmerge.vvm v8, v28, v8, v0 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -913,15 +916,15 @@ define @vdivu_vv_nxv8i64( %va, @vdivu_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vdivu_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vdivu.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -932,21 +935,22 @@ define @vdivu_vx_nxv8i64( %va, i64 %b) { define @vdivu_vi_nxv8i64_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv8i64_0: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.i v16, -7 ; CHECK-NEXT: lui a0, 131072 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: addi a0, zero, 32 -; CHECK-NEXT: vsll.vx v24, v24, a0 -; CHECK-NEXT: vmv.v.i v0, 1 -; CHECK-NEXT: vsll.vx v0, v0, a0 -; CHECK-NEXT: vsrl.vx v0, v0, a0 -; CHECK-NEXT: vor.vv v24, v0, v24 -; CHECK-NEXT: vmulhu.vv v24, v8, v24 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: addi a0, zero, 1 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero +; CHECK-NEXT: vmv.v.i v24, -7 +; CHECK-NEXT: vmulhu.vv v16, v8, v16 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v24, v24, a0 -; CHECK-NEXT: vmseq.vi v0, v16, 1 -; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0 +; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vmseq.vi v0, v24, 1 +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll index 4bc5060..e8460a0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll @@ -699,15 +699,15 @@ define @vmax_vv_nxv1i64( %va, @vmax_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vmax_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vmax.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -744,15 +744,15 @@ define @vmax_vv_nxv2i64( %va, @vmax_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vmax_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vmax.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -789,15 +789,15 @@ define @vmax_vv_nxv4i64( %va, @vmax_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vmax_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vmax.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -834,15 +834,15 @@ define @vmax_vv_nxv8i64( %va, @vmax_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vmax_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmax.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll index 2161d61..19fc081 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll @@ -699,15 +699,15 @@ define @vmax_vv_nxv1i64( %va, @vmax_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vmax_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vmaxu.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -744,15 +744,15 @@ define @vmax_vv_nxv2i64( %va, @vmax_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vmax_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vmaxu.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -789,15 +789,15 @@ define @vmax_vv_nxv4i64( %va, @vmax_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vmax_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vmaxu.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -834,15 +834,15 @@ define @vmax_vv_nxv8i64( %va, @vmax_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vmax_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmaxu.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll index 6863296..44091fd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll @@ -699,15 +699,15 @@ define @vmin_vv_nxv1i64( %va, @vmin_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vmin_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vmin.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -744,15 +744,15 @@ define @vmin_vv_nxv2i64( %va, @vmin_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vmin_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vmin.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -789,15 +789,15 @@ define @vmin_vv_nxv4i64( %va, @vmin_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vmin_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vmin.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -834,15 +834,15 @@ define @vmin_vv_nxv8i64( %va, @vmin_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vmin_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmin.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll index f6fb12c..6442f82 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll @@ -699,15 +699,15 @@ define @vmin_vv_nxv1i64( %va, @vmin_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vmin_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vminu.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -744,15 +744,15 @@ define @vmin_vv_nxv2i64( %va, @vmin_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vmin_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vminu.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -789,15 +789,15 @@ define @vmin_vv_nxv4i64( %va, @vmin_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vmin_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vminu.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -834,15 +834,15 @@ define @vmin_vv_nxv8i64( %va, @vmin_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vmin_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vminu.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll index 60f2ec4..fbca7f4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll @@ -644,15 +644,15 @@ define @vmul_vv_nxv1i64( %va, @vmul_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vmul_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vmul.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -686,15 +686,15 @@ define @vmul_vv_nxv2i64( %va, @vmul_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vmul_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vmul.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -728,15 +728,15 @@ define @vmul_vv_nxv4i64( %va, @vmul_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vmul_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vmul.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -770,15 +770,15 @@ define @vmul_vv_nxv8i64( %va, @vmul_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vmul_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmul.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll index 9a8bbb0..b6ee5e7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll @@ -886,15 +886,15 @@ define @vor_vx_nxv16i32_2( %va) { define @vor_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vor_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vor.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -942,15 +942,15 @@ define @vor_vx_nxv1i64_2( %va) { define @vor_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vor_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vor.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -998,15 +998,15 @@ define @vor_vx_nxv2i64_2( %va) { define @vor_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vor_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vor.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1054,15 +1054,15 @@ define @vor_vx_nxv4i64_2( %va) { define @vor_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vor_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vor.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll index 2e04b90..46cc6e5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll @@ -1186,20 +1186,21 @@ declare i64 @llvm.vector.reduce.smax.nxv1i64() define i64 @vreduce_smax_nxv1i64( %v) { ; CHECK-LABEL: vreduce_smax_nxv1i64: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: lui a0, 524288 -; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: sw zero, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vredmax.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; CHECK-NEXT: vsrl.vx v25, v25, a1 ; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smax.nxv1i64( %v) ret i64 %red @@ -1228,21 +1229,23 @@ declare i64 @llvm.vector.reduce.smin.nxv1i64() define i64 @vreduce_smin_nxv1i64( %v) { ; CHECK-LABEL: vreduce_smin_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vsrl.vx v25, v25, a1 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: addi a0, zero, -1 +; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: addi a0, a0, -1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v25, v26 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vredmin.vs v25, v8, v25 ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; CHECK-NEXT: vsrl.vx v25, v25, a1 ; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smin.nxv1i64( %v) ret i64 %red @@ -1347,22 +1350,23 @@ declare i64 @llvm.vector.reduce.smax.nxv2i64() define i64 @vreduce_smax_nxv2i64( %v) { ; CHECK-LABEL: vreduce_smax_nxv2i64: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: lui a0, 524288 -; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: sw zero, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu ; CHECK-NEXT: vredmax.vs v25, v8, v25 ; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; CHECK-NEXT: vsrl.vx v25, v25, a1 ; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smax.nxv2i64( %v) ret i64 %red @@ -1393,23 +1397,25 @@ declare i64 @llvm.vector.reduce.smin.nxv2i64() define i64 @vreduce_smin_nxv2i64( %v) { ; CHECK-LABEL: vreduce_smin_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vsrl.vx v25, v25, a1 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: addi a0, zero, -1 +; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: addi a0, a0, -1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v25, v26 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu ; CHECK-NEXT: vredmin.vs v25, v8, v25 ; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; CHECK-NEXT: vsrl.vx v25, v25, a1 ; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smin.nxv2i64( %v) ret i64 %red @@ -1520,22 +1526,23 @@ declare i64 @llvm.vector.reduce.smax.nxv4i64() define i64 @vreduce_smax_nxv4i64( %v) { ; CHECK-LABEL: vreduce_smax_nxv4i64: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: lui a0, 524288 -; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: sw zero, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu ; CHECK-NEXT: vredmax.vs v25, v8, v25 ; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; CHECK-NEXT: vsrl.vx v25, v25, a1 ; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smax.nxv4i64( %v) ret i64 %red @@ -1566,23 +1573,25 @@ declare i64 @llvm.vector.reduce.smin.nxv4i64() define i64 @vreduce_smin_nxv4i64( %v) { ; CHECK-LABEL: vreduce_smin_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vsrl.vx v25, v25, a1 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: addi a0, zero, -1 +; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: addi a0, a0, -1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v25, v26 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu ; CHECK-NEXT: vredmin.vs v25, v8, v25 ; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu ; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; CHECK-NEXT: vsrl.vx v25, v25, a1 ; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smin.nxv4i64( %v) ret i64 %red diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll index 2a79b33..ba37c0c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll @@ -782,15 +782,15 @@ define @vrem_vv_nxv1i64( %va, @vrem_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vrem_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vrem.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -801,18 +801,17 @@ define @vrem_vx_nxv1i64( %va, i64 %b) { define @vrem_vi_nxv1i64_0( %va) { ; CHECK-LABEL: vrem_vi_nxv1i64_0: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: lui a0, 748983 ; CHECK-NEXT: addi a0, a0, -586 -; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: addi a0, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a0 -; CHECK-NEXT: lui a1, 898779 -; CHECK-NEXT: addi a1, a1, 1755 -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: vsll.vx v26, v26, a0 -; CHECK-NEXT: vsrl.vx v26, v26, a0 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: lui a0, 898779 +; CHECK-NEXT: addi a0, a0, 1755 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vmulh.vv v25, v8, v25 ; CHECK-NEXT: addi a0, zero, 63 ; CHECK-NEXT: vsrl.vx v26, v25, a0 @@ -821,6 +820,7 @@ define @vrem_vi_nxv1i64_0( %va) { ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vmul.vx v25, v25, a0 ; CHECK-NEXT: vsub.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -841,15 +841,15 @@ define @vrem_vv_nxv2i64( %va, @vrem_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vrem_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vrem.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -860,18 +860,17 @@ define @vrem_vx_nxv2i64( %va, i64 %b) { define @vrem_vi_nxv2i64_0( %va) { ; CHECK-LABEL: vrem_vi_nxv2i64_0: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: lui a0, 748983 ; CHECK-NEXT: addi a0, a0, -586 -; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: addi a0, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a0 -; CHECK-NEXT: lui a1, 898779 -; CHECK-NEXT: addi a1, a1, 1755 -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: vsll.vx v28, v28, a0 -; CHECK-NEXT: vsrl.vx v28, v28, a0 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: lui a0, 898779 +; CHECK-NEXT: addi a0, a0, 1755 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vmulh.vv v26, v8, v26 ; CHECK-NEXT: addi a0, zero, 63 ; CHECK-NEXT: vsrl.vx v28, v26, a0 @@ -880,6 +879,7 @@ define @vrem_vi_nxv2i64_0( %va) { ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vmul.vx v26, v26, a0 ; CHECK-NEXT: vsub.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -900,15 +900,15 @@ define @vrem_vv_nxv4i64( %va, @vrem_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vrem_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vrem.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -919,18 +919,17 @@ define @vrem_vx_nxv4i64( %va, i64 %b) { define @vrem_vi_nxv4i64_0( %va) { ; CHECK-LABEL: vrem_vi_nxv4i64_0: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: lui a0, 748983 ; CHECK-NEXT: addi a0, a0, -586 -; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: addi a0, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a0 -; CHECK-NEXT: lui a1, 898779 -; CHECK-NEXT: addi a1, a1, 1755 -; CHECK-NEXT: vmv.v.x v12, a1 -; CHECK-NEXT: vsll.vx v12, v12, a0 -; CHECK-NEXT: vsrl.vx v12, v12, a0 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: lui a0, 898779 +; CHECK-NEXT: addi a0, a0, 1755 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vmulh.vv v28, v8, v28 ; CHECK-NEXT: addi a0, zero, 63 ; CHECK-NEXT: vsrl.vx v12, v28, a0 @@ -939,6 +938,7 @@ define @vrem_vi_nxv4i64_0( %va) { ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vmul.vx v28, v28, a0 ; CHECK-NEXT: vsub.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -959,15 +959,15 @@ define @vrem_vv_nxv8i64( %va, @vrem_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vrem_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vrem.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -978,18 +978,17 @@ define @vrem_vx_nxv8i64( %va, i64 %b) { define @vrem_vi_nxv8i64_0( %va) { ; CHECK-LABEL: vrem_vi_nxv8i64_0: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: lui a0, 748983 ; CHECK-NEXT: addi a0, a0, -586 -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a0 -; CHECK-NEXT: addi a0, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a0 -; CHECK-NEXT: lui a1, 898779 -; CHECK-NEXT: addi a1, a1, 1755 -; CHECK-NEXT: vmv.v.x v24, a1 -; CHECK-NEXT: vsll.vx v24, v24, a0 -; CHECK-NEXT: vsrl.vx v24, v24, a0 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: lui a0, 898779 +; CHECK-NEXT: addi a0, a0, 1755 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmulh.vv v16, v8, v16 ; CHECK-NEXT: addi a0, zero, 63 ; CHECK-NEXT: vsrl.vx v24, v16, a0 @@ -998,6 +997,7 @@ define @vrem_vi_nxv8i64_0( %va) { ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vmul.vx v16, v16, a0 ; CHECK-NEXT: vsub.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll index 6fba6c9..6c3eba8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll @@ -781,15 +781,15 @@ define @vremu_vv_nxv1i64( %va, @vremu_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vremu_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vremu.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -800,24 +800,25 @@ define @vremu_vx_nxv1i64( %va, i64 %b) { define @vremu_vi_nxv1i64_0( %va) { ; CHECK-LABEL: vremu_vi_nxv1i64_0: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.i v25, -7 ; CHECK-NEXT: lui a0, 131072 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: addi a0, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a0 -; CHECK-NEXT: vmv.v.i v27, 1 -; CHECK-NEXT: vsll.vx v27, v27, a0 -; CHECK-NEXT: vsrl.vx v27, v27, a0 -; CHECK-NEXT: vor.vv v26, v27, v26 -; CHECK-NEXT: vmulhu.vv v26, v8, v26 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: addi a0, zero, 1 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero +; CHECK-NEXT: vmv.v.i v26, -7 +; CHECK-NEXT: vmulhu.vv v25, v8, v25 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v26, v26, a0 -; CHECK-NEXT: vmseq.vi v0, v25, 1 -; CHECK-NEXT: vmerge.vvm v25, v26, v8, v0 +; CHECK-NEXT: vsrl.vx v25, v25, a0 +; CHECK-NEXT: vmseq.vi v0, v26, 1 +; CHECK-NEXT: vmerge.vvm v25, v25, v8, v0 ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vmul.vx v25, v25, a0 ; CHECK-NEXT: vsub.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -838,15 +839,15 @@ define @vremu_vv_nxv2i64( %va, @vremu_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vremu_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vremu.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -857,24 +858,25 @@ define @vremu_vx_nxv2i64( %va, i64 %b) { define @vremu_vi_nxv2i64_0( %va) { ; CHECK-LABEL: vremu_vi_nxv2i64_0: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.i v26, -7 ; CHECK-NEXT: lui a0, 131072 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: addi a0, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a0 -; CHECK-NEXT: vmv.v.i v30, 1 -; CHECK-NEXT: vsll.vx v30, v30, a0 -; CHECK-NEXT: vsrl.vx v30, v30, a0 -; CHECK-NEXT: vor.vv v28, v30, v28 -; CHECK-NEXT: vmulhu.vv v28, v8, v28 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: addi a0, zero, 1 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero +; CHECK-NEXT: vmv.v.i v28, -7 +; CHECK-NEXT: vmulhu.vv v26, v8, v26 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v28, v28, a0 -; CHECK-NEXT: vmseq.vi v0, v26, 1 -; CHECK-NEXT: vmerge.vvm v26, v28, v8, v0 +; CHECK-NEXT: vsrl.vx v26, v26, a0 +; CHECK-NEXT: vmseq.vi v0, v28, 1 +; CHECK-NEXT: vmerge.vvm v26, v26, v8, v0 ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vmul.vx v26, v26, a0 ; CHECK-NEXT: vsub.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -895,15 +897,15 @@ define @vremu_vv_nxv4i64( %va, @vremu_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vremu_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vremu.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -914,24 +916,25 @@ define @vremu_vx_nxv4i64( %va, i64 %b) { define @vremu_vi_nxv4i64_0( %va) { ; CHECK-LABEL: vremu_vi_nxv4i64_0: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.i v28, -7 ; CHECK-NEXT: lui a0, 131072 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: addi a0, zero, 32 -; CHECK-NEXT: vsll.vx v12, v12, a0 -; CHECK-NEXT: vmv.v.i v16, 1 -; CHECK-NEXT: vsll.vx v16, v16, a0 -; CHECK-NEXT: vsrl.vx v16, v16, a0 -; CHECK-NEXT: vor.vv v12, v16, v12 -; CHECK-NEXT: vmulhu.vv v12, v8, v12 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: addi a0, zero, 1 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero +; CHECK-NEXT: vmv.v.i v12, -7 +; CHECK-NEXT: vmulhu.vv v28, v8, v28 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v12, v12, a0 -; CHECK-NEXT: vmseq.vi v0, v28, 1 -; CHECK-NEXT: vmerge.vvm v28, v12, v8, v0 +; CHECK-NEXT: vsrl.vx v28, v28, a0 +; CHECK-NEXT: vmseq.vi v0, v12, 1 +; CHECK-NEXT: vmerge.vvm v28, v28, v8, v0 ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vmul.vx v28, v28, a0 ; CHECK-NEXT: vsub.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -952,15 +955,15 @@ define @vremu_vv_nxv8i64( %va, @vremu_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vremu_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vremu.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -971,24 +974,25 @@ define @vremu_vx_nxv8i64( %va, i64 %b) { define @vremu_vi_nxv8i64_0( %va) { ; CHECK-LABEL: vremu_vi_nxv8i64_0: ; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.i v16, -7 ; CHECK-NEXT: lui a0, 131072 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: addi a0, zero, 32 -; CHECK-NEXT: vsll.vx v24, v24, a0 -; CHECK-NEXT: vmv.v.i v0, 1 -; CHECK-NEXT: vsll.vx v0, v0, a0 -; CHECK-NEXT: vsrl.vx v0, v0, a0 -; CHECK-NEXT: vor.vv v24, v0, v24 -; CHECK-NEXT: vmulhu.vv v24, v8, v24 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: addi a0, zero, 1 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero +; CHECK-NEXT: vmv.v.i v24, -7 +; CHECK-NEXT: vmulhu.vv v16, v8, v16 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v24, v24, a0 -; CHECK-NEXT: vmseq.vi v0, v16, 1 -; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0 +; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vmseq.vi v0, v24, 1 +; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0 ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vmul.vx v16, v16, a0 ; CHECK-NEXT: vsub.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll index 2a080aa..bd12140 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll @@ -436,15 +436,15 @@ define @vrsub_vi_nxv16i32_0( %va) { define @vrsub_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vrsub_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vsub.vv v8, v25, v8 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -467,15 +467,15 @@ define @vrsub_vi_nxv1i64_0( %va) { define @vrsub_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vrsub_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vsub.vv v8, v26, v8 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -498,15 +498,15 @@ define @vrsub_vi_nxv2i64_0( %va) { define @vrsub_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vrsub_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vsub.vv v8, v28, v8 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -529,15 +529,15 @@ define @vrsub_vi_nxv4i64_0( %va) { define @vrsub_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vrsub_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vsub.vv v8, v16, v8 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll index 4317a45..09aba05 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll @@ -626,15 +626,15 @@ define @vmerge_vv_nxv1i64( %va, @vmerge_xv_nxv1i64( %va, i64 %b, %cond) { ; CHECK-LABEL: vmerge_xv_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vmerge.vvm v8, v8, v25, v0 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -667,15 +667,15 @@ define @vmerge_vv_nxv2i64( %va, @vmerge_xv_nxv2i64( %va, i64 %b, %cond) { ; CHECK-LABEL: vmerge_xv_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vmerge.vvm v8, v8, v26, v0 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -708,15 +708,15 @@ define @vmerge_vv_nxv4i64( %va, @vmerge_xv_nxv4i64( %va, i64 %b, %cond) { ; CHECK-LABEL: vmerge_xv_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vmerge.vvm v8, v8, v28, v0 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -749,15 +749,15 @@ define @vmerge_vv_nxv8i64( %va, @vmerge_xv_nxv8i64( %va, i64 %b, %cond) { ; CHECK-LABEL: vmerge_xv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll index 6860f2e..f9bd5f8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll @@ -436,15 +436,15 @@ define @vshl_vx_nxv16i32_0( %va) { define @vshl_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vshl_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vsll.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -480,15 +480,15 @@ define @vshl_vx_nxv1i64_1( %va) { define @vshl_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vshl_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vsll.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -524,15 +524,15 @@ define @vshl_vx_nxv2i64_1( %va) { define @vshl_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vshl_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vsll.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -568,15 +568,15 @@ define @vshl_vx_nxv4i64_1( %va) { define @vshl_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vshl_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vsll.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll index 819dded..545991d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll @@ -60,13 +60,16 @@ define @vsplat_nxv8i64_3() { define @vsplat_nxv8i64_4() { ; RV32V-LABEL: vsplat_nxv8i64_4: ; RV32V: # %bb.0: +; RV32V-NEXT: addi sp, sp, -16 +; RV32V-NEXT: .cfi_def_cfa_offset 16 +; RV32V-NEXT: sw zero, 12(sp) ; RV32V-NEXT: lui a0, 1028096 ; RV32V-NEXT: addi a0, a0, -1281 -; RV32V-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; RV32V-NEXT: vmv.v.x v8, a0 -; RV32V-NEXT: addi a0, zero, 32 -; RV32V-NEXT: vsll.vx v8, v8, a0 -; RV32V-NEXT: vsrl.vx v8, v8, a0 +; RV32V-NEXT: sw a0, 8(sp) +; RV32V-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; RV32V-NEXT: addi a0, sp, 8 +; RV32V-NEXT: vlse64.v v8, (a0), zero +; RV32V-NEXT: addi sp, sp, 16 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vsplat_nxv8i64_4: @@ -85,14 +88,14 @@ define @vsplat_nxv8i64_4() { define @vsplat_nxv8i64_5(i64 %a) { ; RV32V-LABEL: vsplat_nxv8i64_5: ; RV32V: # %bb.0: -; RV32V-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; RV32V-NEXT: vmv.v.x v8, a1 -; RV32V-NEXT: addi a1, zero, 32 -; RV32V-NEXT: vsll.vx v8, v8, a1 -; RV32V-NEXT: vmv.v.x v16, a0 -; RV32V-NEXT: vsll.vx v16, v16, a1 -; RV32V-NEXT: vsrl.vx v16, v16, a1 -; RV32V-NEXT: vor.vv v8, v16, v8 +; RV32V-NEXT: addi sp, sp, -16 +; RV32V-NEXT: .cfi_def_cfa_offset 16 +; RV32V-NEXT: sw a1, 12(sp) +; RV32V-NEXT: sw a0, 8(sp) +; RV32V-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; RV32V-NEXT: addi a0, sp, 8 +; RV32V-NEXT: vlse64.v v8, (a0), zero +; RV32V-NEXT: addi sp, sp, 16 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vsplat_nxv8i64_5: @@ -186,14 +189,17 @@ define @vadd_vx_nxv8i64_9( %v) { define @vadd_vx_nxv8i64_10( %v) { ; RV32V-LABEL: vadd_vx_nxv8i64_10: ; RV32V: # %bb.0: +; RV32V-NEXT: addi sp, sp, -16 +; RV32V-NEXT: .cfi_def_cfa_offset 16 +; RV32V-NEXT: sw zero, 12(sp) ; RV32V-NEXT: lui a0, 1028096 ; RV32V-NEXT: addi a0, a0, -1281 -; RV32V-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; RV32V-NEXT: vmv.v.x v16, a0 -; RV32V-NEXT: addi a0, zero, 32 -; RV32V-NEXT: vsll.vx v16, v16, a0 -; RV32V-NEXT: vsrl.vx v16, v16, a0 +; RV32V-NEXT: sw a0, 8(sp) +; RV32V-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; RV32V-NEXT: addi a0, sp, 8 +; RV32V-NEXT: vlse64.v v16, (a0), zero ; RV32V-NEXT: vadd.vv v8, v8, v16 +; RV32V-NEXT: addi sp, sp, 16 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vadd_vx_nxv8i64_10: @@ -213,17 +219,18 @@ define @vadd_vx_nxv8i64_10( %v) { define @vadd_vx_nxv8i64_11( %v) { ; RV32V-LABEL: vadd_vx_nxv8i64_11: ; RV32V: # %bb.0: +; RV32V-NEXT: addi sp, sp, -16 +; RV32V-NEXT: .cfi_def_cfa_offset 16 +; RV32V-NEXT: addi a0, zero, 1 +; RV32V-NEXT: sw a0, 12(sp) +; RV32V-NEXT: lui a0, 1028096 +; RV32V-NEXT: addi a0, a0, -1281 +; RV32V-NEXT: sw a0, 8(sp) ; RV32V-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; RV32V-NEXT: vmv.v.i v16, 1 -; RV32V-NEXT: addi a0, zero, 32 -; RV32V-NEXT: vsll.vx v16, v16, a0 -; RV32V-NEXT: lui a1, 1028096 -; RV32V-NEXT: addi a1, a1, -1281 -; RV32V-NEXT: vmv.v.x v24, a1 -; RV32V-NEXT: vsll.vx v24, v24, a0 -; RV32V-NEXT: vsrl.vx v24, v24, a0 -; RV32V-NEXT: vor.vv v16, v24, v16 +; RV32V-NEXT: addi a0, sp, 8 +; RV32V-NEXT: vlse64.v v16, (a0), zero ; RV32V-NEXT: vadd.vv v8, v8, v16 +; RV32V-NEXT: addi sp, sp, 16 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vadd_vx_nxv8i64_11: @@ -243,15 +250,15 @@ define @vadd_vx_nxv8i64_11( %v) { define @vadd_vx_nxv8i64_12( %v, i64 %a) { ; RV32V-LABEL: vadd_vx_nxv8i64_12: ; RV32V: # %bb.0: -; RV32V-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; RV32V-NEXT: vmv.v.x v16, a1 -; RV32V-NEXT: addi a1, zero, 32 -; RV32V-NEXT: vsll.vx v16, v16, a1 -; RV32V-NEXT: vmv.v.x v24, a0 -; RV32V-NEXT: vsll.vx v24, v24, a1 -; RV32V-NEXT: vsrl.vx v24, v24, a1 -; RV32V-NEXT: vor.vv v16, v24, v16 +; RV32V-NEXT: addi sp, sp, -16 +; RV32V-NEXT: .cfi_def_cfa_offset 16 +; RV32V-NEXT: sw a1, 12(sp) +; RV32V-NEXT: sw a0, 8(sp) +; RV32V-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; RV32V-NEXT: addi a0, sp, 8 +; RV32V-NEXT: vlse64.v v16, (a0), zero ; RV32V-NEXT: vadd.vv v8, v8, v16 +; RV32V-NEXT: addi sp, sp, 16 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vadd_vx_nxv8i64_12: @@ -287,11 +294,14 @@ define @vsplat_nxv8i64_13(i32 %a) { define @vsplat_nxv8i64_14(i32 %a) { ; RV32V-LABEL: vsplat_nxv8i64_14: ; RV32V: # %bb.0: -; RV32V-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; RV32V-NEXT: vmv.v.x v8, a0 -; RV32V-NEXT: addi a0, zero, 32 -; RV32V-NEXT: vsll.vx v8, v8, a0 -; RV32V-NEXT: vsrl.vx v8, v8, a0 +; RV32V-NEXT: addi sp, sp, -16 +; RV32V-NEXT: .cfi_def_cfa_offset 16 +; RV32V-NEXT: sw zero, 12(sp) +; RV32V-NEXT: sw a0, 8(sp) +; RV32V-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; RV32V-NEXT: addi a0, sp, 8 +; RV32V-NEXT: vlse64.v v8, (a0), zero +; RV32V-NEXT: addi sp, sp, 16 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vsplat_nxv8i64_14: diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll index 7cfc7ff..4accc94 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll @@ -626,15 +626,15 @@ define @vsra_vv_nxv1i64( %va, @vsra_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vsra_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vsra.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -680,15 +680,15 @@ define @vsra_vv_nxv2i64( %va, @vsra_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vsra_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vsra.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -734,15 +734,15 @@ define @vsra_vv_nxv4i64( %va, @vsra_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vsra_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vsra.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -788,15 +788,15 @@ define @vsra_vv_nxv8i64( %va, @vsra_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vsra_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vsra.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll index ad83ab2..e3b6595 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll @@ -436,15 +436,15 @@ define @vsrl_vx_nxv16i32_0( %va) { define @vsrl_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vsrl_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vsrl.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -480,15 +480,15 @@ define @vsrl_vx_nxv1i64_1( %va) { define @vsrl_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vsrl_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vsrl.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -524,15 +524,15 @@ define @vsrl_vx_nxv2i64_1( %va) { define @vsrl_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vsrl_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vsrl.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -568,15 +568,15 @@ define @vsrl_vx_nxv4i64_1( %va) { define @vsrl_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vsrl_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vsrl.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll index fb5ddf0..f6fb784 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll @@ -659,15 +659,15 @@ define @vsub_vv_nxv1i64( %va, @vsub_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vsub_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vsub.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -701,15 +701,15 @@ define @vsub_vv_nxv2i64( %va, @vsub_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vsub_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vsub.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -743,15 +743,15 @@ define @vsub_vv_nxv4i64( %va, @vsub_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vsub_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vsub.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -785,15 +785,15 @@ define @vsub_vv_nxv8i64( %va, @vsub_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vsub_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vsub.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll index 0946721..8b13912 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll @@ -1076,15 +1076,15 @@ define @vxor_vv_nxv1i64( %va, @vxor_vx_nxv1i64( %va, i64 %b) { ; CHECK-LABEL: vxor_vx_nxv1i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vxor.vv v8, v8, v25 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1142,15 +1142,15 @@ define @vxor_vv_nxv2i64( %va, @vxor_vx_nxv2i64( %va, i64 %b) { ; CHECK-LABEL: vxor_vx_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vxor.vv v8, v8, v26 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1208,15 +1208,15 @@ define @vxor_vv_nxv4i64( %va, @vxor_vx_nxv4i64( %va, i64 %b) { ; CHECK-LABEL: vxor_vx_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.v.x v28, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v12, a0 -; CHECK-NEXT: vsll.vx v12, v12, a1 -; CHECK-NEXT: vsrl.vx v12, v12, a1 -; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vxor.vv v8, v8, v28 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1274,15 +1274,15 @@ define @vxor_vv_nxv8i64( %va, @vxor_vx_nxv8i64( %va, i64 %b) { ; CHECK-LABEL: vxor_vx_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v16, v16, a1 -; CHECK-NEXT: vmv.v.x v24, a0 -; CHECK-NEXT: vsll.vx v24, v24, a1 -; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vxor.vv v8, v8, v16 +; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer -- 2.7.4