From 262115d1dbd1098839d54bf08c5c89f42a248ebc Mon Sep 17 00:00:00 2001 From: rth Date: Fri, 15 Oct 1999 06:38:02 +0000 Subject: [PATCH] * 1750a.md (movstrqi): Add missing output reload constraint. (call_value): Likewise. * a29k.md (cpxxx patterns): Add missing match_operator mode. (jmpfdec): Add missing inout reload constraint. * elxsi.md (addsi patterns): Add missing output reload constraint. (move from sp): Use @ alternates. (call_value): No constraint on output. * fr30.md (movsi_pop): Add missing output reload constraint. (movsf_constant_store): Likewise. (splits): Remove constraints. (subsi3): Add missing mode. * i370.md (cmpstrsi+1): Add missing output reload constraint. (call_value): Likewise. * i960.md (cmpinc/cmpdec patterns): Add inout reload constraints. * m32r.h (PREDICATE_CODES): Add seth_add3_operand. * m32r.md (movsicc_internal): Add output reload constraint. (movstrsi_internal): Add inout reload constraints. * m88k.h (reg_names): Don't declare. (SPECIAL_MODE_PREDICATES): New. * m88k.md (*): Use register_operand not reg_or_0_operand on destinations. * mn10200.h (PREDICATE_CODES): New. * ns32k.md (ffs pattern): Add output reload constraint. * pdp11.md (sob pattern): Add inout reload constraint. * sh.md (splits): Remove constraints. (indirect_jump_scratch, fpu_switch): Add output reload constraint. * v850.md (pattern_is_ok_for_epilogue): Likewise. * vax.md (jgequ pattern): Add inout reload constraint. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@30008 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 31 +++++++++++++++++++++++++++++++ gcc/config/1750a/1750a.md | 4 ++-- gcc/config/a29k/a29k.md | 8 ++++---- gcc/config/elxsi/elxsi.md | 16 +++++++--------- gcc/config/fr30/fr30.md | 20 ++++++++++---------- gcc/config/i370/i370.md | 6 +++--- gcc/config/i960/i960.md | 8 ++++---- gcc/config/m32r/m32r.h | 3 ++- gcc/config/m32r/m32r.md | 6 +++--- gcc/config/m88k/m88k.h | 8 +++++++- gcc/config/m88k/m88k.md | 8 ++++---- gcc/config/mn10200/mn10200.h | 7 +++++++ gcc/config/ns32k/ns32k.md | 2 +- gcc/config/pdp11/pdp11.md | 2 +- gcc/config/sh/sh.md | 14 +++++++------- gcc/config/v850/v850.md | 2 +- gcc/config/vax/vax.md | 2 +- 17 files changed, 95 insertions(+), 52 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c7bb5a9..dfacdb9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,34 @@ +Thu Oct 14 23:19:34 1999 Richard Henderson + + * 1750a.md (movstrqi): Add missing output reload constraint. + (call_value): Likewise. + * a29k.md (cpxxx patterns): Add missing match_operator mode. + (jmpfdec): Add missing inout reload constraint. + * elxsi.md (addsi patterns): Add missing output reload constraint. + (move from sp): Use @ alternates. + (call_value): No constraint on output. + * fr30.md (movsi_pop): Add missing output reload constraint. + (movsf_constant_store): Likewise. + (splits): Remove constraints. + (subsi3): Add missing mode. + * i370.md (cmpstrsi+1): Add missing output reload constraint. + (call_value): Likewise. + * i960.md (cmpinc/cmpdec patterns): Add inout reload constraints. + * m32r.h (PREDICATE_CODES): Add seth_add3_operand. + * m32r.md (movsicc_internal): Add output reload constraint. + (movstrsi_internal): Add inout reload constraints. + * m88k.h (reg_names): Don't declare. + (SPECIAL_MODE_PREDICATES): New. + * m88k.md (*): Use register_operand not reg_or_0_operand + on destinations. + * mn10200.h (PREDICATE_CODES): New. + * ns32k.md (ffs pattern): Add output reload constraint. + * pdp11.md (sob pattern): Add inout reload constraint. + * sh.md (splits): Remove constraints. + (indirect_jump_scratch, fpu_switch): Add output reload constraint. + * v850.md (pattern_is_ok_for_epilogue): Likewise. + * vax.md (jgequ pattern): Add inout reload constraint. + Fri Oct 15 00:05:00 1999 Jeffrey A Law (law@cygnus.com) * configure.in (djgpp): Revert previous patch. diff --git a/gcc/config/1750a/1750a.md b/gcc/config/1750a/1750a.md index 3bea692..f53b77a 100644 --- a/gcc/config/1750a/1750a.md +++ b/gcc/config/1750a/1750a.md @@ -133,7 +133,7 @@ ;; block move. (define_insn "movstrqi" - [(set (match_operand:BLK 0 "mov_memory_operand" "m") + [(set (match_operand:BLK 0 "mov_memory_operand" "=m") (match_operand:BLK 1 "mov_memory_operand" "m")) (use (match_operand:QI 2 "general_operand" "r")) (match_operand 3 "" "") @@ -1352,7 +1352,7 @@ ;; Call subroutine, returning value in operand 0 ;; (which must be a hard register). (define_insn "call_value" - [(set (match_operand 0 "register_operand" "r") + [(set (match_operand 0 "register_operand" "=r") (call (match_operand:QI 1 "memory_operand" "m") (match_operand:QI 2 "general_operand" "g")))] ;; Operand 2 not really used for 1750. diff --git a/gcc/config/a29k/a29k.md b/gcc/config/a29k/a29k.md index aa82c6c..998d892 100644 --- a/gcc/config/a29k/a29k.md +++ b/gcc/config/a29k/a29k.md @@ -337,7 +337,7 @@ ;; CPxxx, DEQ, DGT, DGE, FEQ, FGT, FGE (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (match_operator 3 "comparison_operator" + (match_operator:SI 3 "comparison_operator" [(match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "srcb_operand" "rI")]))] "" @@ -345,7 +345,7 @@ (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (match_operator 3 "fp_comparison_operator" + (match_operator:SI 3 "fp_comparison_operator" [(match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "register_operand" "r")]))] "! TARGET_SOFT_FLOAT" @@ -354,7 +354,7 @@ (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (match_operator 3 "fp_comparison_operator" + (match_operator:SI 3 "fp_comparison_operator" [(match_operand:DF 1 "register_operand" "r") (match_operand:DF 2 "register_operand" "r")]))] "! TARGET_SOFT_FLOAT" @@ -2861,7 +2861,7 @@ ;; JMPFDEC (define_insn "" [(set (pc) - (if_then_else (ge (match_operand:SI 0 "gpc_reg_operand" "r") + (if_then_else (ge (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 0)) (label_ref (match_operand 1 "" "")) (pc))) diff --git a/gcc/config/elxsi/elxsi.md b/gcc/config/elxsi/elxsi.md index b6969e9..9611ac2 100644 --- a/gcc/config/elxsi/elxsi.md +++ b/gcc/config/elxsi/elxsi.md @@ -46,14 +46,14 @@ "add.64\\t.sp,%0") (define_insn "" - [(set (match_operand:SI 0 "register_operand" "r") + [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (reg:SI 15) (match_operand:SI 1 "general_operand" "g")))] "" "ld.32\\t%0,.sp\;add.64\\t%0,%1") (define_insn "" - [(set (match_operand:SI 0 "register_operand" "r") + [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (match_operand:SI 1 "general_operand" "g") (reg:SI 15)))] "" @@ -73,14 +73,12 @@ "ld.32\\t.sp,%0") (define_insn "" - [(set (match_operand:SI 0 "general_operand" "m,r") + [(set (match_operand:SI 0 "nonimmediate_operand" "=m,r") (reg:SI 15))] "" - "* - if (which_alternative == 0) - return \"st.32\\t.sp,%0\"; - return \"ld.32\\t%0,.sp\"; -") + "@ + st.32\\t.sp,%0 + ld.32\\t%0,.sp") ; tstdi is first test insn so that it is the one to match ; a constant argument. @@ -1394,7 +1392,7 @@ if (0) { ") (define_insn "call_value" - [(set (match_operand 0 "" "g") + [(set (match_operand 0 "" "") (call (match_operand:QI 1 "general_operand" "m") (match_operand:QI 2 "general_operand" "g")))] "" diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md index f0ac26a..6618fe3 100644 --- a/gcc/config/fr30/fr30.md +++ b/gcc/config/fr30/fr30.md @@ -149,7 +149,7 @@ ;; Pop a register off the stack (define_insn "movsi_pop" - [(set:SI (match_operand:SI 0 "register_operand" "a") + [(set:SI (match_operand:SI 0 "register_operand" "=a") (mem:SI (post_inc:SI (reg:SI 15))))] "" "ld @r15+, %0" @@ -288,8 +288,8 @@ ;; If we are loading a small negative constant we can save space ;; and time by loading the positive value and then sign extending it. (define_split - [(set (match_operand:SI 0 "register_operand" "r") - (match_operand:SI 1 "immediate_operand" "i"))] + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "immediate_operand" ""))] "INTVAL (operands[1]) <= -1 && INTVAL (operands[1]) >= -128" [(set:SI (match_dup 0) (match_dup 2)) (set:SI (match_dup 0) (sign_extend:SI (subreg:QI (match_dup 0) 0)))] @@ -302,8 +302,8 @@ ;; not have any of its bottom 24 bit set, then we can save time ;; and space by loading the byte value and shifting it into place. (define_split - [(set (match_operand:SI 0 "register_operand" "r") - (match_operand:SI 1 "immediate_operand" "i"))] + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "immediate_operand" ""))] "(INTVAL (operands[1]) < 0) && (INTVAL (operands[1]) & 0x00ffffff == 0)" [(set:SI (match_dup 0) (match_dup 2)) (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (const_int 24))) @@ -319,8 +319,8 @@ ;; range, then we can save time and space by loading the byte value ;; and shifting it into place. (define_split - [(set (match_operand:SI 0 "register_operand" "r") - (match_operand:SI 1 "immediate_operand" "i"))] + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "immediate_operand" ""))] "(INTVAL (operands[1]) > 0x00ffffff) && ((INTVAL (operands[1]) >> exact_log2 (INTVAL (operands[1]) & (- INTVAL (operands[1])))) < 0x100)" [(set:SI (match_dup 0) (match_dup 2)) @@ -528,7 +528,7 @@ ) (define_insn "*movsf_constant_store" - [(set (match_operand:SF 0 "memory_operand" "m") + [(set (match_operand:SF 0 "memory_operand" "=m") (match_operand:SF 1 "immediate_operand" "F"))] "" "* @@ -695,8 +695,8 @@ (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=r") - (minus (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "register_operand" "r")))] + (minus:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "register_operand" "r")))] "" "subn %2, %0" ) diff --git a/gcc/config/i370/i370.md b/gcc/config/i370/i370.md index b6bbf4d..7fba863 100644 --- a/gcc/config/i370/i370.md +++ b/gcc/config/i370/i370.md @@ -552,7 +552,7 @@ check_label_emit (); ; Compare a block that is less than 256 bytes in length. (define_insn "" - [(set (match_operand:SI 0 "register_operand" "d") + [(set (match_operand:SI 0 "register_operand" "=d") (compare (match_operand:BLK 1 "s_operand" "m") (match_operand:BLK 2 "s_operand" "m"))) (use (match_operand:QI 3 "immediate_operand" "I"))] @@ -4598,7 +4598,7 @@ check_label_emit (); ; (define_insn "call_value" - [(set (match_operand 0 "" "rf") + [(set (match_operand 0 "" "=rf") (call (match_operand:QI 1 "memory_operand" "m") (match_operand:SI 2 "general_operand" "i"))) (clobber (reg:SI 2)) @@ -4669,7 +4669,7 @@ check_label_emit (); ) (define_insn "" - [(set (match_operand 0 "" "rf") + [(set (match_operand 0 "" "=rf") (call (mem:QI (match_operand:SI 1 "" "i")) (match_operand:SI 2 "general_operand" "g"))) (clobber (reg:SI 2)) diff --git a/gcc/config/i960/i960.md b/gcc/config/i960/i960.md index 616e979..1e5c112 100644 --- a/gcc/config/i960/i960.md +++ b/gcc/config/i960/i960.md @@ -220,7 +220,7 @@ (define_insn "" [(set (reg:CC 36) (compare (match_operand:SI 0 "arith_operand" "d") - (match_operand:SI 1 "arith_operand" "d"))) + (match_operand:SI 1 "arith_operand" "+d"))) (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))] "0" "cmpinci %0,%1" @@ -229,7 +229,7 @@ (define_insn "" [(set (reg:CC_UNS 36) (compare (match_operand:SI 0 "arith_operand" "d") - (match_operand:SI 1 "arith_operand" "d"))) + (match_operand:SI 1 "arith_operand" "+d"))) (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))] "0" "cmpinco %0,%1" @@ -238,7 +238,7 @@ (define_insn "" [(set (reg:CC 36) (compare (match_operand:SI 0 "arith_operand" "d") - (match_operand:SI 1 "arith_operand" "d"))) + (match_operand:SI 1 "arith_operand" "+d"))) (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))] "0" "cmpdeci %0,%1" @@ -247,7 +247,7 @@ (define_insn "" [(set (reg:CC_UNS 36) (compare (match_operand:SI 0 "arith_operand" "d") - (match_operand:SI 1 "arith_operand" "d"))) + (match_operand:SI 1 "arith_operand" "+d"))) (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))] "0" "cmpdeco %0,%1" diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h index 4e11838..032e089 100644 --- a/gcc/config/m32r/m32r.h +++ b/gcc/config/m32r/m32r.h @@ -1981,7 +1981,8 @@ enum m32r_function_type { "call_address_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \ { "small_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, \ { "m32r_block_immediate_operand",{ CONST_INT }}, \ -{ "large_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, +{ "large_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, \ +{ "seth_add3_operand", { SYMBOL_REF, LABEL_REF, CONST }}, /* Functions declared in m32r.c */ #define XPROTO(ARGS) () diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md index bc01b2a..0ad11f0 100644 --- a/gcc/config/m32r/m32r.md +++ b/gcc/config/m32r/m32r.md @@ -1675,7 +1675,7 @@ ;; Generate the conditional instructions based on how the carry flag is examined. (define_insn "*movsicc_internal" - [(set (match_operand:SI 0 "register_operand" "r") + [(set (match_operand:SI 0 "register_operand" "=r") (if_then_else:SI (match_operand 1 "carry_compare_operand" "") (match_operand:SI 2 "conditional_move_operand" "O") (match_operand:SI 3 "conditional_move_operand" "O") @@ -1781,8 +1781,8 @@ ;; Insn generated by block moves (define_insn "movstrsi_internal" - [(set (mem:BLK (match_operand:SI 0 "register_operand" "r")) ;; destination - (mem:BLK (match_operand:SI 1 "register_operand" "r"))) ;; source + [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r")) ;; destination + (mem:BLK (match_operand:SI 1 "register_operand" "+r"))) ;; source (use (match_operand:SI 2 "m32r_block_immediate_operand" "J"));; # bytes to move (set (match_dup 0) (plus:SI (match_dup 0) (minus:SI (match_dup 2) (const_int 4)))) (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2))) diff --git a/gcc/config/m88k/m88k.h b/gcc/config/m88k/m88k.h index 707bd3c..2937857 100644 --- a/gcc/config/m88k/m88k.h +++ b/gcc/config/m88k/m88k.h @@ -157,7 +157,6 @@ extern int target_flags; /* -m compiler switches */ extern int frame_pointer_needed; /* current function has a FP */ extern int flag_delayed_branch; /* -fdelayed-branch */ extern int flag_pic; /* -fpic */ -extern char * reg_names[]; /* Specify the default monitors. The meaning of these values can be obtained by doing "grep MONITOR_GCC *m88k*". Generally, the @@ -1496,6 +1495,13 @@ extern struct rtx_def *m88k_va_arg (); {"equality_op", {EQ, NE}}, \ {"pc_or_label_ref", {PC, LABEL_REF}}, +/* A list of predicates that do special things with modes, and so + should not elicit warnings for VOIDmode match_operand. */ + +#define SPECIAL_MODE_PREDICATES \ + "partial_ccmode_register_operand", \ + "pc_or_label_ref", + /* The case table contains either words or branch instructions. This says which. We always claim that the vector is PC-relative. It is position independent when -fpic is used. */ diff --git a/gcc/config/m88k/m88k.md b/gcc/config/m88k/m88k.md index a82a528..85d944e 100644 --- a/gcc/config/m88k/m88k.md +++ b/gcc/config/m88k/m88k.md @@ -2556,7 +2556,7 @@ ;; Add with carry insns. (define_insn "" - [(parallel [(set (match_operand:SI 0 "reg_or_0_operand" "=r") + [(parallel [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (match_operand:SI 1 "reg_or_0_operand" "rO") (match_operand:SI 2 "reg_or_0_operand" "rO"))) (set (reg:CC 0) @@ -2572,7 +2572,7 @@ "addu.co %#r0,%r0,%r1") (define_insn "" - [(set (match_operand:SI 0 "reg_or_0_operand" "=r") + [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (match_operand:SI 1 "reg_or_0_operand" "rO") (unspec:SI [(match_operand:SI 2 "reg_or_0_operand" "rO") (reg:CC 0)] 0)))] @@ -2676,7 +2676,7 @@ ;; Subtract with carry insns. (define_insn "" - [(parallel [(set (match_operand:SI 0 "reg_or_0_operand" "=r") + [(parallel [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO") (match_operand:SI 2 "reg_or_0_operand" "rO"))) (set (reg:CC 0) @@ -2692,7 +2692,7 @@ "subu.co %#r0,%r0,%r1") (define_insn "" - [(set (match_operand:SI 0 "reg_or_0_operand" "=r") + [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO") (unspec:SI [(match_operand:SI 2 "reg_or_0_operand" "rO") (reg:CC 0)] 1)))] diff --git a/gcc/config/mn10200/mn10200.h b/gcc/config/mn10200/mn10200.h index 1ade6f2..6f9cceb 100644 --- a/gcc/config/mn10200/mn10200.h +++ b/gcc/config/mn10200/mn10200.h @@ -1060,6 +1060,13 @@ do { char dstr[30]; \ #define FILE_ASM_OP "\t.file\n" +#define PREDICATE_CODES \ + {"call_address_operand", { SYMBOL_REF, REG }}, \ + {"constant_memory_operand", { MEM }}, \ + {"extendpsi_operand", { PLUS, CONST_INT, CONST_DOUBLE, CONST, \ + SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM }}, \ + {"nshift_operator", { ASHIFTRT, LSHIFTRT, ASHIFT }}, + extern void asm_file_start (); extern void print_operand (); extern void print_operand_address (); diff --git a/gcc/config/ns32k/ns32k.md b/gcc/config/ns32k/ns32k.md index dfe6629..4763324 100644 --- a/gcc/config/ns32k/ns32k.md +++ b/gcc/config/ns32k/ns32k.md @@ -2904,7 +2904,7 @@ ;; ffs instructions (define_insn "" - [(set (match_operand:SI 0 "general_operand" "ro") + [(set (match_operand:SI 0 "general_operand" "=ro") (minus:SI (plus:SI (ffs:SI (zero_extract:SI (match_operand:SI 1 "general_operand" "g") diff --git a/gcc/config/pdp11/pdp11.md b/gcc/config/pdp11/pdp11.md index 217e314..469e8e2 100644 --- a/gcc/config/pdp11/pdp11.md +++ b/gcc/config/pdp11/pdp11.md @@ -223,7 +223,7 @@ (define_insn "" [(set (pc) (if_then_else - (ne (plus:HI (match_operand:HI 0 "register_operand" "r") + (ne (plus:HI (match_operand:HI 0 "register_operand" "+r") (const_int -1)) (const_int 0)) (label_ref (match_operand 1 "" "")) diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index ac3d3b0..8ed9829 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -2943,17 +2943,17 @@ (set_attr "type" "pcload,move")]) (define_split - [(set (match_operand:SI 0 "register_operand" "y") - (match_operand:SI 1 "immediate_operand" "I")) - (clobber (match_operand:SI 2 "register_operand" "r"))] + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "immediate_operand" "")) + (clobber (match_operand:SI 2 "register_operand" ""))] "" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (match_dup 2))] "") (define_split - [(set (match_operand:SI 0 "register_operand" "y") - (match_operand:SI 1 "memory_operand" ">")) + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "memory_operand" "")) (clobber (reg:SI 0))] "" [(set (match_dup 0) (match_dup 1))] @@ -2992,7 +2992,7 @@ ;; This one has the additional purpose to record a possible scratch register ;; for the following branch. (define_insn "indirect_jump_scratch" - [(set (match_operand 0 "register_operand" "r") + [(set (match_operand 0 "register_operand" "=r") (unspec [(match_operand 1 "const_int_operand" "")] 4))] "" "" @@ -3791,7 +3791,7 @@ ;; The gp_fpul type for r/!c might look a bit odd, but it actually schedules ;; like a gpr <-> fpul move. (define_insn "fpu_switch" - [(set (match_operand:PSI 0 "register_operand" "c,c,r,c,c,r,m,r") + [(set (match_operand:PSI 0 "register_operand" "=c,c,r,c,c,r,m,r") (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c"))] "! reload_completed || true_regnum (operands[0]) != FPSCR_REG || GET_CODE (operands[1]) != MEM diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md index 5214d16..d1df676 100644 --- a/gcc/config/v850/v850.md +++ b/gcc/config/v850/v850.md @@ -1255,7 +1255,7 @@ [(return) (set (reg:SI 3) (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i"))) - (set (match_operand:SI 2 "register_is_ok_for_epilogue" "r") + (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r") (mem:SI (plus:SI (reg:SI 3) (match_operand:SI 3 "immediate_operand" "i"))))])] "TARGET_PROLOG_FUNCTION && TARGET_V850" diff --git a/gcc/config/vax/vax.md b/gcc/config/vax/vax.md index ead6607..0f48a31 100644 --- a/gcc/config/vax/vax.md +++ b/gcc/config/vax/vax.md @@ -1825,7 +1825,7 @@ (define_insn "" [(set (pc) (if_then_else - (ne (match_operand:SI 0 "general_operand" "g") + (ne (match_operand:SI 0 "general_operand" "+g") (const_int 0)) (label_ref (match_operand 1 "" "")) (pc))) -- 2.7.4