From 25fbb716f1aefafb731082d5d571ea040d5d51a4 Mon Sep 17 00:00:00 2001 From: Xingyu Wu Date: Thu, 15 Dec 2022 14:17:59 +0800 Subject: [PATCH] clk: starfive: Change divider value of cpu_core clock Change divider value to make sure the frequency is half of PLL0. Signed-off-by: Xingyu Wu --- drivers/clk/starfive/clk-starfive-jh7110-gen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-gen.c b/drivers/clk/starfive/clk-starfive-jh7110-gen.c index cf974d2ffa38..d852c0a2d01f 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-gen.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-gen.c @@ -392,7 +392,7 @@ static int __init clk_starfive_jh7110_probe(struct platform_device *pdev) if (PLL0_DEFAULT_FREQ >= PLL0_FREQ_1500_VALUE) { struct clk *cpu_core = priv->reg[JH7110_CPU_CORE].hw.clk; - if (clk_set_rate(cpu_core, PLL0_FREQ_1500_VALUE / 2)) { + if (clk_set_rate(cpu_core, clk_get_rate(pll0_clk) / 2)) { dev_err(&pdev->dev, "set cpu_core rate failed\n"); goto failed_set; } -- 2.34.1