From 25983cad31969e3003eef77bc03a6700f46899d2 Mon Sep 17 00:00:00 2001 From: Evgeny Voevodin Date: Wed, 21 Nov 2012 11:43:04 +0400 Subject: [PATCH] TCG: Use gen_opc_pc from context instead of global variable. Signed-off-by: Evgeny Voevodin Signed-off-by: Blue Swirl --- target-alpha/translate.c | 4 ++-- target-arm/translate.c | 4 ++-- target-cris/translate.c | 6 +++--- target-i386/translate.c | 9 +++++---- target-lm32/translate.c | 4 ++-- target-m68k/translate.c | 4 ++-- target-microblaze/translate.c | 4 ++-- target-mips/translate.c | 4 ++-- target-openrisc/translate.c | 4 ++-- target-ppc/translate.c | 4 ++-- target-s390x/translate.c | 4 ++-- target-sh4/translate.c | 4 ++-- target-sparc/translate.c | 4 ++-- target-unicore32/translate.c | 4 ++-- target-xtensa/translate.c | 4 ++-- 15 files changed, 34 insertions(+), 33 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 4045f78..bcde367 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -3412,7 +3412,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env, while (lj < j) gen_opc_instr_start[lj++] = 0; } - gen_opc_pc[lj] = ctx.pc; + tcg_ctx.gen_opc_pc[lj] = ctx.pc; gen_opc_instr_start[lj] = 1; gen_opc_icount[lj] = num_insns; } @@ -3551,5 +3551,5 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model) void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb, int pc_pos) { - env->pc = gen_opc_pc[pc_pos]; + env->pc = tcg_ctx.gen_opc_pc[pc_pos]; } diff --git a/target-arm/translate.c b/target-arm/translate.c index c42110a..8ea8bba 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -9840,7 +9840,7 @@ static inline void gen_intermediate_code_internal(CPUARMState *env, while (lj < j) gen_opc_instr_start[lj++] = 0; } - gen_opc_pc[lj] = dc->pc; + tcg_ctx.gen_opc_pc[lj] = dc->pc; gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1); gen_opc_instr_start[lj] = 1; gen_opc_icount[lj] = num_insns; @@ -10043,6 +10043,6 @@ void cpu_dump_state(CPUARMState *env, FILE *f, fprintf_function cpu_fprintf, void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb, int pc_pos) { - env->regs[15] = gen_opc_pc[pc_pos]; + env->regs[15] = tcg_ctx.gen_opc_pc[pc_pos]; env->condexec_bits = gen_opc_condexec_bits[pc_pos]; } diff --git a/target-cris/translate.c b/target-cris/translate.c index 0b0e86d..745cd7a 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3305,9 +3305,9 @@ gen_intermediate_code_internal(CPUCRISState *env, TranslationBlock *tb, } } if (dc->delayed_branch == 1) { - gen_opc_pc[lj] = dc->ppc | 1; + tcg_ctx.gen_opc_pc[lj] = dc->ppc | 1; } else { - gen_opc_pc[lj] = dc->pc; + tcg_ctx.gen_opc_pc[lj] = dc->pc; } gen_opc_instr_start[lj] = 1; gen_opc_icount[lj] = num_insns; @@ -3621,5 +3621,5 @@ CRISCPU *cpu_cris_init(const char *cpu_model) void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos) { - env->pc = gen_opc_pc[pc_pos]; + env->pc = tcg_ctx.gen_opc_pc[pc_pos]; } diff --git a/target-i386/translate.c b/target-i386/translate.c index 8e676ba..aea843c 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7990,7 +7990,7 @@ static inline void gen_intermediate_code_internal(CPUX86State *env, while (lj < j) gen_opc_instr_start[lj++] = 0; } - gen_opc_pc[lj] = pc_ptr; + tcg_ctx.gen_opc_pc[lj] = pc_ptr; gen_opc_cc_op[lj] = dc->cc_op; gen_opc_instr_start[lj] = 1; gen_opc_icount[lj] = num_insns; @@ -8081,15 +8081,16 @@ void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos) qemu_log("RESTORE:\n"); for(i = 0;i <= pc_pos; i++) { if (gen_opc_instr_start[i]) { - qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]); + qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, + tcg_ctx.gen_opc_pc[i]); } } qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n", - pc_pos, gen_opc_pc[pc_pos] - tb->cs_base, + pc_pos, tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base, (uint32_t)tb->cs_base); } #endif - env->eip = gen_opc_pc[pc_pos] - tb->cs_base; + env->eip = tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base; cc_op = gen_opc_cc_op[pc_pos]; if (cc_op != CC_OP_DYNAMIC) env->cc_op = cc_op; diff --git a/target-lm32/translate.c b/target-lm32/translate.c index af98649..fcafb06 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -1054,7 +1054,7 @@ static void gen_intermediate_code_internal(CPULM32State *env, gen_opc_instr_start[lj++] = 0; } } - gen_opc_pc[lj] = dc->pc; + tcg_ctx.gen_opc_pc[lj] = dc->pc; gen_opc_instr_start[lj] = 1; gen_opc_icount[lj] = num_insns; } @@ -1172,7 +1172,7 @@ void cpu_dump_state(CPULM32State *env, FILE *f, fprintf_function cpu_fprintf, void restore_state_to_opc(CPULM32State *env, TranslationBlock *tb, int pc_pos) { - env->pc = gen_opc_pc[pc_pos]; + env->pc = tcg_ctx.gen_opc_pc[pc_pos]; } void lm32_translate_init(void) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index b13be48..74772dd 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3021,7 +3021,7 @@ gen_intermediate_code_internal(CPUM68KState *env, TranslationBlock *tb, while (lj < j) gen_opc_instr_start[lj++] = 0; } - gen_opc_pc[lj] = dc->pc; + tcg_ctx.gen_opc_pc[lj] = dc->pc; gen_opc_instr_start[lj] = 1; gen_opc_icount[lj] = num_insns; } @@ -3121,5 +3121,5 @@ void cpu_dump_state(CPUM68KState *env, FILE *f, fprintf_function cpu_fprintf, void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, int pc_pos) { - env->pc = gen_opc_pc[pc_pos]; + env->pc = tcg_ctx.gen_opc_pc[pc_pos]; } diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index cce4494..6803f73 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1790,7 +1790,7 @@ gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb, while (lj < j) gen_opc_instr_start[lj++] = 0; } - gen_opc_pc[lj] = dc->pc; + tcg_ctx.gen_opc_pc[lj] = dc->pc; gen_opc_instr_start[lj] = 1; gen_opc_icount[lj] = num_insns; } @@ -2014,5 +2014,5 @@ MicroBlazeCPU *cpu_mb_init(const char *cpu_model) void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos) { - env->sregs[SR_PC] = gen_opc_pc[pc_pos]; + env->sregs[SR_PC] = tcg_ctx.gen_opc_pc[pc_pos]; } diff --git a/target-mips/translate.c b/target-mips/translate.c index 71c55bc..e1ea968 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15581,7 +15581,7 @@ gen_intermediate_code_internal (CPUMIPSState *env, TranslationBlock *tb, while (lj < j) gen_opc_instr_start[lj++] = 0; } - gen_opc_pc[lj] = ctx.pc; + tcg_ctx.gen_opc_pc[lj] = ctx.pc; gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK; gen_opc_btarget[lj] = ctx.btarget; gen_opc_instr_start[lj] = 1; @@ -16002,7 +16002,7 @@ void cpu_state_reset(CPUMIPSState *env) void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, int pc_pos) { - env->active_tc.PC = gen_opc_pc[pc_pos]; + env->active_tc.PC = tcg_ctx.gen_opc_pc[pc_pos]; env->hflags &= ~MIPS_HFLAG_BMASK; env->hflags |= gen_opc_hflags[pc_pos]; switch (env->hflags & MIPS_HFLAG_BMASK_BASE) { diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index f14da7b..b7ad6a4 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1710,7 +1710,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu, gen_opc_instr_start[k++] = 0; } } - gen_opc_pc[k] = dc->pc; + tcg_ctx.gen_opc_pc[k] = dc->pc; gen_opc_instr_start[k] = 1; gen_opc_icount[k] = num_insns; } @@ -1832,5 +1832,5 @@ void cpu_dump_state(CPUOpenRISCState *env, FILE *f, void restore_state_to_opc(CPUOpenRISCState *env, TranslationBlock *tb, int pc_pos) { - env->pc = gen_opc_pc[pc_pos]; + env->pc = tcg_ctx.gen_opc_pc[pc_pos]; } diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 987b04e..276edc8 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9682,7 +9682,7 @@ static inline void gen_intermediate_code_internal(CPUPPCState *env, while (lj < j) gen_opc_instr_start[lj++] = 0; } - gen_opc_pc[lj] = ctx.nip; + tcg_ctx.gen_opc_pc[lj] = ctx.nip; gen_opc_instr_start[lj] = 1; gen_opc_icount[lj] = num_insns; } @@ -9810,5 +9810,5 @@ void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb) void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos) { - env->nip = gen_opc_pc[pc_pos]; + env->nip = tcg_ctx.gen_opc_pc[pc_pos]; } diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 993f207..ff2868f 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -5163,7 +5163,7 @@ static inline void gen_intermediate_code_internal(CPUS390XState *env, gen_opc_instr_start[lj++] = 0; } } - gen_opc_pc[lj] = dc.pc; + tcg_ctx.gen_opc_pc[lj] = dc.pc; gen_opc_cc_op[lj] = dc.cc_op; gen_opc_instr_start[lj] = 1; gen_opc_icount[lj] = num_insns; @@ -5240,7 +5240,7 @@ void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb) void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos) { int cc_op; - env->psw.addr = gen_opc_pc[pc_pos]; + env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos]; cc_op = gen_opc_cc_op[pc_pos]; if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) { env->cc_op = cc_op; diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 5497ded..4def163 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -2005,7 +2005,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb, while (ii < i) gen_opc_instr_start[ii++] = 0; } - gen_opc_pc[ii] = ctx.pc; + tcg_ctx.gen_opc_pc[ii] = ctx.pc; gen_opc_hflags[ii] = ctx.flags; gen_opc_instr_start[ii] = 1; gen_opc_icount[ii] = num_insns; @@ -2088,6 +2088,6 @@ void gen_intermediate_code_pc(CPUSH4State * env, struct TranslationBlock *tb) void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb, int pc_pos) { - env->pc = gen_opc_pc[pc_pos]; + env->pc = tcg_ctx.gen_opc_pc[pc_pos]; env->flags = gen_opc_hflags[pc_pos]; } diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 2ae8036..4f3a844 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -5284,7 +5284,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb, lj++; while (lj < j) gen_opc_instr_start[lj++] = 0; - gen_opc_pc[lj] = dc->pc; + tcg_ctx.gen_opc_pc[lj] = dc->pc; gen_opc_npc[lj] = dc->npc; gen_opc_instr_start[lj] = 1; gen_opc_icount[lj] = num_insns; @@ -5478,7 +5478,7 @@ void gen_intermediate_code_init(CPUSPARCState *env) void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb, int pc_pos) { target_ulong npc; - env->pc = gen_opc_pc[pc_pos]; + env->pc = tcg_ctx.gen_opc_pc[pc_pos]; npc = gen_opc_npc[pc_pos]; if (npc == 1) { /* dynamic NPC: already stored */ diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 052bb45..32a4265 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -2006,7 +2006,7 @@ static inline void gen_intermediate_code_internal(CPUUniCore32State *env, gen_opc_instr_start[lj++] = 0; } } - gen_opc_pc[lj] = dc->pc; + tcg_ctx.gen_opc_pc[lj] = dc->pc; gen_opc_instr_start[lj] = 1; gen_opc_icount[lj] = num_insns; } @@ -2203,5 +2203,5 @@ void cpu_dump_state(CPUUniCore32State *env, FILE *f, void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb, int pc_pos) { - env->regs[31] = gen_opc_pc[pc_pos]; + env->regs[31] = tcg_ctx.gen_opc_pc[pc_pos]; } diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index e5a3f49..21126fc 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -2900,7 +2900,7 @@ static void gen_intermediate_code_internal( gen_opc_instr_start[lj++] = 0; } } - gen_opc_pc[lj] = dc.pc; + tcg_ctx.gen_opc_pc[lj] = dc.pc; gen_opc_instr_start[lj] = 1; gen_opc_icount[lj] = insn_count; } @@ -3028,5 +3028,5 @@ void cpu_dump_state(CPUXtensaState *env, FILE *f, fprintf_function cpu_fprintf, void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, int pc_pos) { - env->pc = gen_opc_pc[pc_pos]; + env->pc = tcg_ctx.gen_opc_pc[pc_pos]; } -- 2.7.4