From 2589888ce969fe0254cd69c200afe535e2cdfb79 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Thu, 23 Jul 2020 16:53:30 +0200 Subject: [PATCH] radeonsi/tmz: add tmz variant of sctx::wait_mem_scratch MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Marek Olšák Part-of: --- src/gallium/drivers/radeonsi/si_pipe.c | 18 ++++++++++++++++-- src/gallium/drivers/radeonsi/si_pipe.h | 1 + src/gallium/drivers/radeonsi/si_state_draw.c | 12 ++++++++---- 3 files changed, 25 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 34fb638..0a91ca4 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -196,6 +196,7 @@ static void si_destroy_context(struct pipe_context *context) si_resource_reference(&sctx->scratch_buffer, NULL); si_resource_reference(&sctx->compute_scratch_buffer, NULL); si_resource_reference(&sctx->wait_mem_scratch, NULL); + si_resource_reference(&sctx->wait_mem_scratch_tmz, NULL); si_resource_reference(&sctx->small_prim_cull_info_buf, NULL); if (sctx->cs_preamble_state) @@ -619,6 +620,17 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign sscreen->info.tcc_cache_line_size); if (!sctx->wait_mem_scratch) goto fail; + + if (sscreen->info.has_tmz_support) { + sctx->wait_mem_scratch_tmz = + si_aligned_buffer_create(screen, + SI_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL | + PIPE_RESOURCE_FLAG_ENCRYPTED, + PIPE_USAGE_DEFAULT, 8, + sscreen->info.tcc_cache_line_size); + if (!sctx->wait_mem_scratch_tmz) + goto fail; + } } /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads @@ -692,10 +704,12 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign assert(sctx->gfx_cs->current.cdw == sctx->initial_gfx_cs_size); /* Initialize per-context buffers. */ - if (sctx->wait_mem_scratch) { + if (sctx->wait_mem_scratch) si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4, V_370_MEM, V_370_ME, &sctx->wait_mem_number); - } + if (sctx->wait_mem_scratch_tmz) + si_cp_write_data(sctx, sctx->wait_mem_scratch_tmz, 0, 4, V_370_MEM, V_370_ME, + &sctx->wait_mem_number); if (sctx->chip_class == GFX7) { /* Clear the NULL constant buffer, because loads should return zeros. diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 900b371..5514389 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -951,6 +951,7 @@ struct si_context { struct si_shader_ctx_state fixed_func_tcs_shader; /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */ struct si_resource *wait_mem_scratch; + struct si_resource *wait_mem_scratch_tmz; unsigned wait_mem_number; uint16_t prefetch_L2_mask; diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index a88311e..6ac271c 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1112,6 +1112,8 @@ void gfx10_emit_cache_flush(struct si_context *ctx) } if (cb_db_event) { + struct si_resource* wait_mem_scratch = unlikely(ctx->ws->cs_is_secure(cs)) ? + ctx->wait_mem_scratch_tmz : ctx->wait_mem_scratch; /* CB/DB flush and invalidate (or possibly just a wait for a * meta flush) via RELEASE_MEM. * @@ -1123,7 +1125,7 @@ void gfx10_emit_cache_flush(struct si_context *ctx) uint64_t va; /* Do the flush (enqueue the event and wait for it). */ - va = ctx->wait_mem_scratch->gpu_address; + va = wait_mem_scratch->gpu_address; ctx->wait_mem_number++; /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */ @@ -1146,7 +1148,7 @@ void gfx10_emit_cache_flush(struct si_context *ctx) S_490_GL1_INV(gl1_inv) | S_490_GL2_INV(gl2_inv) | S_490_GL2_WB(gl2_wb) | S_490_SEQ(gcr_seq), EOP_DST_SEL_MEM, EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, - EOP_DATA_SEL_VALUE_32BIT, ctx->wait_mem_scratch, va, ctx->wait_mem_number, + EOP_DATA_SEL_VALUE_32BIT, wait_mem_scratch, va, ctx->wait_mem_number, SI_NOT_QUERY); si_cp_wait_mem(ctx, ctx->gfx_cs, va, ctx->wait_mem_number, 0xffffffff, WAIT_REG_MEM_EQUAL); } @@ -1340,12 +1342,14 @@ void si_emit_cache_flush(struct si_context *sctx) } /* Do the flush (enqueue the event and wait for it). */ - va = sctx->wait_mem_scratch->gpu_address; + struct si_resource* wait_mem_scratch = unlikely(sctx->ws->cs_is_secure(cs)) ? + sctx->wait_mem_scratch_tmz : sctx->wait_mem_scratch; + va = wait_mem_scratch->gpu_address; sctx->wait_mem_number++; si_cp_release_mem(sctx, cs, cb_db_event, tc_flags, EOP_DST_SEL_MEM, EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_VALUE_32BIT, - sctx->wait_mem_scratch, va, sctx->wait_mem_number, SI_NOT_QUERY); + wait_mem_scratch, va, sctx->wait_mem_number, SI_NOT_QUERY); si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff, WAIT_REG_MEM_EQUAL); } -- 2.7.4