From 2578df3c59a191c91a81b267d25b57d59901c19f Mon Sep 17 00:00:00 2001 From: =?utf8?q?=C5=81ukasz=20Stelmach?= Date: Wed, 2 Aug 2023 09:26:29 +0200 Subject: [PATCH] samsung: tizen_riscv: Reorganise environment defaults for RISC-V MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Rename, reorganize and use the default envitonment settings in the header file for both VisionFive2 and QEMU targets. Change-Id: Ic6ab2c5b2dc146d232a54eab6727afce845c1353 Signed-off-by: Łukasz Stelmach --- include/configs/qemu-riscv.h | 2 ++ include/configs/starfive-visionfive2.h | 2 +- .../{tizen_visionfive2.h => tizen_riscv.h} | 23 +++++++++++++++---- 3 files changed, 21 insertions(+), 6 deletions(-) rename include/samsung/{tizen_visionfive2.h => tizen_riscv.h} (72%) diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index d81e5d6c86..671a00a8a9 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -7,6 +7,7 @@ #define __CONFIG_H #include +#include #define CONFIG_SYS_SDRAM_BASE 0x80000000 @@ -37,6 +38,7 @@ "qemu " #define CONFIG_EXTRA_ENV_SETTINGS \ + TIZEN_ENV_SETTING \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr_r=0x84000000\0" \ diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index 7c259ec99d..7da8f2e4d1 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -8,7 +8,7 @@ #ifndef _STARFIVE_VISIONFIVE2_H #define _STARFIVE_VISIONFIVE2_H -#include +#include #define RISCV_MMODE_TIMERBASE 0x2000000 #define RISCV_MMODE_TIMER_FREQ 4000000 diff --git a/include/samsung/tizen_visionfive2.h b/include/samsung/tizen_riscv.h similarity index 72% rename from include/samsung/tizen_visionfive2.h rename to include/samsung/tizen_riscv.h index 8bf09744c9..1226beea96 100644 --- a/include/samsung/tizen_visionfive2.h +++ b/include/samsung/tizen_riscv.h @@ -6,8 +6,22 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_TIZEN_VISIONFIVE2_H -#define __CONFIG_TIZEN_VISIONFIVE2_H +#ifndef __CONFIG_TIZEN_RISCV_H +#define __CONFIG_TIZEN_RISCV_H + +#ifdef CONFIG_TARGET_STARFIVE_VISIONFIVE2 +#define TIZEN_TARGET_ENV_SETTING \ + "bootdevnum=1\0" \ + "bootdevtype=mmc\0" \ + "" +#elif defined(CONFIG_TARGET_QEMU_VIRT) +#define TIZEN_TARGET_ENV_SETTING \ + "bootdevnum=0\0" \ + "bootdevtype=virtio\0" \ + "" +#else /* CONFIG_TARGET_* */ +#define TIZEN_TARGET_ENV_SETTING "" +#endif /* CONFIG_TARGET_* */ #define CLEAR_REBOOT_PARAM \ "mw.l ${rebootparam_addr} ${normal_val} ; " \ @@ -19,8 +33,8 @@ #define KERNEL_NAME "Image" #define TIZEN_ENV_SETTING \ + TIZEN_TARGET_ENV_SETTING \ "kernel=" KERNEL_NAME "\0" \ - "bootdevnum=1\0" \ "bootpart=3\0" \ "rootpart=5\0" \ "informpart=0xb\0" \ @@ -36,11 +50,10 @@ "ramdiskpart=9\0" \ "part=9\0" \ "bootmode=ramdisk\0" \ - "bootdevtype=mmc\0" \ "tfm=setenv bootmode download; run bootcmd\0" \ "tizen_bootarg= \0" \ "opts=loglevel=7\0" \ "reboot_param_clear=" CLEAR_REBOOT_PARAM "\0" \ "" -#endif /* __CONFIG_TIZEN_VISIONFIVE2_H */ +#endif /* __CONFIG_TIZEN_RISCV_H */ -- 2.34.1