From 254f4fa5738c03316bc2da13a5e363dd139318b4 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Mon, 26 Sep 2022 19:12:19 +0100 Subject: [PATCH] radv: increase gfx1100/gfx1101 physical vgprs MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit https://reviews.llvm.org/D134522 Signed-off-by: Rhys Perry Reviewed-by: Daniel Schürmann Reviewed-by: Marek Olšák Part-of: --- src/amd/vulkan/radv_shader.c | 5 ++++- src/amd/vulkan/winsys/null/radv_null_winsys.c | 7 ++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 0c328e4..94275b7 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -2801,6 +2801,7 @@ radv_get_max_waves(const struct radv_device *device, struct radv_shader *shader, { struct radeon_info *info = &device->physical_device->rad_info; enum amd_gfx_level gfx_level = info->gfx_level; + enum radeon_family family = info->family; uint8_t wave_size = shader->info.wave_size; struct ac_shader_config *conf = &shader->config; unsigned max_simd_waves; @@ -2827,7 +2828,9 @@ radv_get_max_waves(const struct radv_device *device, struct radv_shader *shader, if (conf->num_vgprs) { unsigned physical_vgprs = info->num_physical_wave64_vgprs_per_simd * (64 / wave_size); unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4); - if (gfx_level == GFX10_3) + if (family == CHIP_GFX1100 || family == CHIP_GFX1101) + vgprs = util_align_npot(vgprs, wave_size == 32 ? 24 : 12); + else if (gfx_level == GFX10_3) vgprs = align(vgprs, wave_size == 32 ? 16 : 8); max_simd_waves = MIN2(max_simd_waves, physical_vgprs / vgprs); } diff --git a/src/amd/vulkan/winsys/null/radv_null_winsys.c b/src/amd/vulkan/winsys/null/radv_null_winsys.c index c7bc1f3..0a3f7e2 100644 --- a/src/amd/vulkan/winsys/null/radv_null_winsys.c +++ b/src/amd/vulkan/winsys/null/radv_null_winsys.c @@ -127,7 +127,12 @@ radv_null_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *info) else info->num_physical_sgprs_per_simd = 512; - info->num_physical_wave64_vgprs_per_simd = info->gfx_level >= GFX10 ? 512 : 256; + if (info->family == CHIP_GFX1100 || info->family == CHIP_GFX1101) + info->num_physical_wave64_vgprs_per_simd = 768; + else if (info->gfx_level >= GFX10) + info->num_physical_wave64_vgprs_per_simd = 512; + else + info->num_physical_wave64_vgprs_per_simd = 256; info->num_simd_per_compute_unit = info->gfx_level >= GFX10 ? 2 : 4; info->lds_size_per_workgroup = info->gfx_level >= GFX10 ? 128 * 1024 : 64 * 1024; info->lds_encode_granularity = info->gfx_level >= GFX7 ? 128 * 4 : 64 * 4; -- 2.7.4