From 254c5246e9204f4d799f41c09068243e3a308177 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Sun, 14 Nov 2021 09:25:00 -0500 Subject: [PATCH] [DAGCombiner] match inverted/swapped patterns for vselect of mask of signbit This was noted as a follow-up to D113212 / D113426: 4fc1fc4005f7 7e30404c3b6c 11522cfcad6b https://alive2.llvm.org/ce/z/e4o96b The canonicalization rules for these IR patterns are complicated, and we were not matching the expected forms in 2 out of the 3 cases. We can make codegen more robust by matching the swapped forms (and that will also work if these patterns are created late). --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 27 ++-- llvm/test/CodeGen/AArch64/cmp-select-sign.ll | 6 +- llvm/test/CodeGen/AArch64/vselect-constants.ll | 15 +- llvm/test/CodeGen/X86/vselect-zero.ll | 212 +++++++++---------------- 4 files changed, 98 insertions(+), 162 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 6f111fc..e6b2dbe 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -9557,11 +9557,17 @@ static SDValue foldVSelectToSignBitSplatMask(SDNode *N, SelectionDAG &DAG) { if (VT != Cond0.getValueType()) return SDValue(); - // TODO: Check for the swapped variants of the following patterns. We can't - // be sure what form is chosen as canonical in IR. + // Match a signbit check of Cond0 as "Cond0 s<0". Swap select operands if the + // compare is inverted from that pattern ("Cond0 s> -1"). + if (CC == ISD::SETLT && isNullOrNullSplat(Cond1)) + ; // This is the pattern we are looking for. + else if (CC == ISD::SETGT && isAllOnesOrAllOnesSplat(Cond1)) + std::swap(N1, N2); + else + return SDValue(); // (Cond0 s< 0) ? N1 : 0 --> (Cond0 s>> BW-1) & N1 - if (CC == ISD::SETLT && isNullOrNullSplat(Cond1) && isNullOrNullSplat(N2)) { + if (isNullOrNullSplat(N2)) { SDLoc DL(N); SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, VT); SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); @@ -9569,26 +9575,23 @@ static SDValue foldVSelectToSignBitSplatMask(SDNode *N, SelectionDAG &DAG) { } // (Cond0 s< 0) ? -1 : N2 --> (Cond0 s>> BW-1) | N2 - if (CC == ISD::SETLT && isNullOrNullSplat(Cond1) && - isAllOnesOrAllOnesSplat(N1)) { + if (isAllOnesOrAllOnesSplat(N1)) { SDLoc DL(N); SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, VT); SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); return DAG.getNode(ISD::OR, DL, VT, Sra, N2); } - // If the comparison is testing for a positive value, we have to invert - // the sign bit mask, so only do that transform if the target has a bitwise - // 'and not' instruction (the invert is free). - // (Cond0 s> -1) ? N1 : 0 --> ~(Cond0 s>> BW-1) & N1 + // If we have to invert the sign bit mask, only do that transform if the + // target has a bitwise 'and not' instruction (the invert is free). + // (Cond0 s< -0) ? 0 : N2 --> ~(Cond0 s>> BW-1) & N2 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - if (CC == ISD::SETGT && isAllOnesOrAllOnesSplat(Cond1) && - isNullOrNullSplat(N2) && TLI.hasAndNot(N2)) { + if (isNullOrNullSplat(N1) && TLI.hasAndNot(N1)) { SDLoc DL(N); SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, VT); SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); SDValue Not = DAG.getNOT(DL, Sra, VT); - return DAG.getNode(ISD::AND, DL, VT, Not, N1); + return DAG.getNode(ISD::AND, DL, VT, Not, N2); } // TODO: There's another pattern in this family, but it may require diff --git a/llvm/test/CodeGen/AArch64/cmp-select-sign.ll b/llvm/test/CodeGen/AArch64/cmp-select-sign.ll index 90d2830..dce2183 100644 --- a/llvm/test/CodeGen/AArch64/cmp-select-sign.ll +++ b/llvm/test/CodeGen/AArch64/cmp-select-sign.ll @@ -213,12 +213,10 @@ define <4 x i32> @not_sign_4xi32(<4 x i32> %a) { define <4 x i32> @not_sign_4xi32_2(<4 x i32> %a) { ; CHECK-LABEL: not_sign_4xi32_2: ; CHECK: // %bb.0: -; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff ; CHECK-NEXT: adrp x8, .LCPI17_0 -; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s +; CHECK-NEXT: sshr v0.4s, v0.4s, #31 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_0] -; CHECK-NEXT: and v1.16b, v0.16b, v1.16b -; CHECK-NEXT: orn v0.16b, v1.16b, v0.16b +; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret %c = icmp sgt <4 x i32> %a, %res = select <4 x i1> %c, <4 x i32> , <4 x i32> diff --git a/llvm/test/CodeGen/AArch64/vselect-constants.ll b/llvm/test/CodeGen/AArch64/vselect-constants.ll index f95b34e..332d110 100644 --- a/llvm/test/CodeGen/AArch64/vselect-constants.ll +++ b/llvm/test/CodeGen/AArch64/vselect-constants.ll @@ -209,9 +209,8 @@ define <16 x i8> @signbit_mask_v16i8(<16 x i8> %a, <16 x i8> %b) { define <16 x i8> @signbit_mask_swap_v16i8(<16 x i8> %a, <16 x i8> %b) { ; CHECK-LABEL: signbit_mask_swap_v16i8: ; CHECK: // %bb.0: -; CHECK-NEXT: movi v2.2d, #0xffffffffffffffff -; CHECK-NEXT: cmgt v0.16b, v0.16b, v2.16b -; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b +; CHECK-NEXT: sshr v0.16b, v0.16b, #7 +; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret %cond = icmp sgt <16 x i8> %a, %r = select <16 x i1> %cond, <16 x i8> zeroinitializer, <16 x i8> %b @@ -278,10 +277,8 @@ define <8 x i16> @signbit_setmask_v8i16(<8 x i16> %a, <8 x i16> %b) { define <8 x i16> @signbit_setmask_swap_v8i16(<8 x i16> %a, <8 x i16> %b) { ; CHECK-LABEL: signbit_setmask_swap_v8i16: ; CHECK: // %bb.0: -; CHECK-NEXT: movi v2.2d, #0xffffffffffffffff -; CHECK-NEXT: cmgt v0.8h, v0.8h, v2.8h -; CHECK-NEXT: and v1.16b, v1.16b, v0.16b -; CHECK-NEXT: orn v0.16b, v1.16b, v0.16b +; CHECK-NEXT: sshr v0.8h, v0.8h, #15 +; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret %cond = icmp sgt <8 x i16> %a, %r = select <8 x i1> %cond, <8 x i16> %b, <8 x i16> @@ -348,8 +345,8 @@ define <4 x i32> @not_signbit_mask_v4i32(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @not_signbit_mask_swap_v4i32(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: not_signbit_mask_swap_v4i32: ; CHECK: // %bb.0: -; CHECK-NEXT: cmlt v0.4s, v0.4s, #0 -; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b +; CHECK-NEXT: cmge v0.4s, v0.4s, #0 +; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret %cond = icmp slt <4 x i32> %a, zeroinitializer %r = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %b diff --git a/llvm/test/CodeGen/X86/vselect-zero.ll b/llvm/test/CodeGen/X86/vselect-zero.ll index 290561f..e00f06c 100644 --- a/llvm/test/CodeGen/X86/vselect-zero.ll +++ b/llvm/test/CodeGen/X86/vselect-zero.ll @@ -345,38 +345,30 @@ define <2 x i64> @signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) { define <2 x i64> @signbit_mask_swap_v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE2-LABEL: signbit_mask_swap_v2i64: ; SSE2: # %bb.0: -; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [18446744071562067967,18446744071562067967] -; SSE2-NEXT: movdqa %xmm0, %xmm3 -; SSE2-NEXT: pcmpgtd %xmm2, %xmm3 -; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm2, %xmm0 -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] -; SSE2-NEXT: pand %xmm4, %xmm2 -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] -; SSE2-NEXT: por %xmm2, %xmm0 -; SSE2-NEXT: pandn %xmm1, %xmm0 +; SSE2-NEXT: psrad $31, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: retq ; ; SSE42-LABEL: signbit_mask_swap_v2i64: ; SSE42: # %bb.0: -; SSE42-NEXT: pcmpeqd %xmm2, %xmm2 -; SSE42-NEXT: pcmpgtq %xmm2, %xmm0 -; SSE42-NEXT: pandn %xmm1, %xmm0 +; SSE42-NEXT: pxor %xmm2, %xmm2 +; SSE42-NEXT: pcmpgtq %xmm0, %xmm2 +; SSE42-NEXT: pand %xmm1, %xmm2 +; SSE42-NEXT: movdqa %xmm2, %xmm0 ; SSE42-NEXT: retq ; ; AVX-LABEL: signbit_mask_swap_v2i64: ; AVX: # %bb.0: -; AVX-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 -; AVX-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm0 -; AVX-NEXT: vpandn %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm0 +; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq ; ; AVX512-LABEL: signbit_mask_swap_v2i64: ; AVX512: # %bb.0: -; AVX512-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 -; AVX512-NEXT: vpcmpleq %xmm2, %xmm0, %k1 -; AVX512-NEXT: vmovdqa64 %xmm1, %xmm0 {%k1} {z} +; AVX512-NEXT: vpsraq $63, %xmm0, %xmm0 +; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: retq %cond = icmp sgt <2 x i64> %a, %r = select <2 x i1> %cond, <2 x i64> zeroinitializer, <2 x i64> %b @@ -497,35 +489,31 @@ define <8 x i32> @signbit_mask_v8i32(<8 x i32> %a, <8 x i32> %b) { define <8 x i32> @signbit_mask_swap_v8i32(<8 x i32> %a, <8 x i32> %b) { ; SSE-LABEL: signbit_mask_swap_v8i32: ; SSE: # %bb.0: -; SSE-NEXT: pcmpeqd %xmm4, %xmm4 -; SSE-NEXT: pcmpgtd %xmm4, %xmm0 -; SSE-NEXT: pandn %xmm2, %xmm0 -; SSE-NEXT: pcmpgtd %xmm4, %xmm1 -; SSE-NEXT: pandn %xmm3, %xmm1 +; SSE-NEXT: psrad $31, %xmm0 +; SSE-NEXT: pand %xmm2, %xmm0 +; SSE-NEXT: psrad $31, %xmm1 +; SSE-NEXT: pand %xmm3, %xmm1 ; SSE-NEXT: retq ; ; AVX1-LABEL: signbit_mask_swap_v8i32: ; AVX1: # %bb.0: -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 -; AVX1-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3 -; AVX1-NEXT: vpcmpgtd %xmm3, %xmm2, %xmm2 -; AVX1-NEXT: vpcmpgtd %xmm3, %xmm0, %xmm0 -; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 -; AVX1-NEXT: vandnps %ymm1, %ymm0, %ymm0 +; AVX1-NEXT: vpsrad $31, %xmm0, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 +; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: retq ; ; AVX2-LABEL: signbit_mask_swap_v8i32: ; AVX2: # %bb.0: -; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 -; AVX2-NEXT: vpcmpgtd %ymm2, %ymm0, %ymm0 -; AVX2-NEXT: vpandn %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpsrad $31, %ymm0, %ymm0 +; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: signbit_mask_swap_v8i32: ; AVX512: # %bb.0: -; AVX512-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 -; AVX512-NEXT: vpcmpled %ymm2, %ymm0, %k1 -; AVX512-NEXT: vmovdqa32 %ymm1, %ymm0 {%k1} {z} +; AVX512-NEXT: vpsrad $31, %ymm0, %ymm0 +; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq %cond = icmp sgt <8 x i32> %a, %r = select <8 x i1> %cond, <8 x i32> zeroinitializer, <8 x i32> %b @@ -614,34 +602,25 @@ define <16 x i8> @signbit_setmask_v16i8(<16 x i8> %a, <16 x i8> %b) { define <16 x i8> @signbit_setmask_swap_v16i8(<16 x i8> %a, <16 x i8> %b) { ; SSE-LABEL: signbit_setmask_swap_v16i8: ; SSE: # %bb.0: -; SSE-NEXT: pcmpeqd %xmm2, %xmm2 -; SSE-NEXT: pcmpgtb %xmm2, %xmm0 -; SSE-NEXT: pxor %xmm2, %xmm0 -; SSE-NEXT: por %xmm1, %xmm0 +; SSE-NEXT: pxor %xmm2, %xmm2 +; SSE-NEXT: pcmpgtb %xmm0, %xmm2 +; SSE-NEXT: por %xmm1, %xmm2 +; SSE-NEXT: movdqa %xmm2, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: signbit_setmask_swap_v16i8: ; AVX: # %bb.0: -; AVX-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 -; AVX-NEXT: vpcmpgtb %xmm2, %xmm0, %xmm0 -; AVX-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq ; -; AVX512F-LABEL: signbit_setmask_swap_v16i8: -; AVX512F: # %bb.0: -; AVX512F-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 -; AVX512F-NEXT: vpcmpgtb %xmm2, %xmm0, %xmm0 -; AVX512F-NEXT: vpternlogq $222, %xmm2, %xmm1, %xmm0 -; AVX512F-NEXT: retq -; -; AVX512DQBW-LABEL: signbit_setmask_swap_v16i8: -; AVX512DQBW: # %bb.0: -; AVX512DQBW-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 -; AVX512DQBW-NEXT: vpcmpgtb %xmm2, %xmm0, %k1 -; AVX512DQBW-NEXT: vmovdqu8 %xmm1, %xmm2 {%k1} -; AVX512DQBW-NEXT: vmovdqa %xmm2, %xmm0 -; AVX512DQBW-NEXT: retq +; AVX512-LABEL: signbit_setmask_swap_v16i8: +; AVX512: # %bb.0: +; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX512-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0 +; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: retq %cond = icmp sgt <16 x i8> %a, %r = select <16 x i1> %cond, <16 x i8> %b, <16 x i8> ret <16 x i8> %r @@ -890,70 +869,47 @@ define <4 x i64> @signbit_setmask_v4i64(<4 x i64> %a, <4 x i64> %b) { define <4 x i64> @signbit_setmask_swap_v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE2-LABEL: signbit_setmask_swap_v4i64: ; SSE2: # %bb.0: -; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648] -; SSE2-NEXT: pxor %xmm8, %xmm0 -; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [18446744071562067967,18446744071562067967] -; SSE2-NEXT: movdqa %xmm0, %xmm6 -; SSE2-NEXT: pcmpgtd %xmm5, %xmm6 -; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm5, %xmm0 -; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3] -; SSE2-NEXT: pand %xmm7, %xmm4 -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3] -; SSE2-NEXT: por %xmm4, %xmm0 -; SSE2-NEXT: pcmpeqd %xmm4, %xmm4 -; SSE2-NEXT: pxor %xmm4, %xmm0 +; SSE2-NEXT: psrad $31, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE2-NEXT: por %xmm2, %xmm0 -; SSE2-NEXT: pxor %xmm8, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: pcmpgtd %xmm5, %xmm2 -; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm2[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm5, %xmm1 -; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm1[1,1,3,3] -; SSE2-NEXT: pand %xmm6, %xmm5 -; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] -; SSE2-NEXT: por %xmm5, %xmm1 -; SSE2-NEXT: pxor %xmm4, %xmm1 +; SSE2-NEXT: psrad $31, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE2-NEXT: por %xmm3, %xmm1 ; SSE2-NEXT: retq ; ; SSE42-LABEL: signbit_setmask_swap_v4i64: ; SSE42: # %bb.0: -; SSE42-NEXT: pcmpeqd %xmm4, %xmm4 -; SSE42-NEXT: pcmpgtq %xmm4, %xmm0 -; SSE42-NEXT: pxor %xmm4, %xmm0 -; SSE42-NEXT: por %xmm2, %xmm0 -; SSE42-NEXT: pcmpgtq %xmm4, %xmm1 -; SSE42-NEXT: pxor %xmm4, %xmm1 -; SSE42-NEXT: por %xmm3, %xmm1 +; SSE42-NEXT: pxor %xmm4, %xmm4 +; SSE42-NEXT: pxor %xmm5, %xmm5 +; SSE42-NEXT: pcmpgtq %xmm0, %xmm5 +; SSE42-NEXT: por %xmm2, %xmm5 +; SSE42-NEXT: pcmpgtq %xmm1, %xmm4 +; SSE42-NEXT: por %xmm3, %xmm4 +; SSE42-NEXT: movdqa %xmm5, %xmm0 +; SSE42-NEXT: movdqa %xmm4, %xmm1 ; SSE42-NEXT: retq ; ; AVX1-LABEL: signbit_setmask_swap_v4i64: ; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 -; AVX1-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3 -; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2 -; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2 -; AVX1-NEXT: vpcmpgtq %xmm3, %xmm0, %xmm0 -; AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2 +; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: retq ; ; AVX2-LABEL: signbit_setmask_swap_v4i64: ; AVX2: # %bb.0: -; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 -; AVX2-NEXT: vpcmpgtq %ymm2, %ymm0, %ymm0 -; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vpcmpgtq %ymm0, %ymm2, %ymm0 ; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: signbit_setmask_swap_v4i64: ; AVX512: # %bb.0: -; AVX512-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 -; AVX512-NEXT: vpcmpgtq %ymm2, %ymm0, %k1 -; AVX512-NEXT: vmovdqa64 %ymm1, %ymm2 {%k1} -; AVX512-NEXT: vmovdqa %ymm2, %ymm0 +; AVX512-NEXT: vpsraq $63, %ymm0, %ymm0 +; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq %cond = icmp sgt <4 x i64> %a, %r = select <4 x i1> %cond, <4 x i64> %b, <4 x i64> @@ -1014,32 +970,21 @@ define <8 x i16> @not_signbit_mask_v8i16(<8 x i16> %a, <8 x i16> %b) { define <8 x i16> @not_signbit_mask_swap_v8i16(<8 x i16> %a, <8 x i16> %b) { ; SSE-LABEL: not_signbit_mask_swap_v8i16: ; SSE: # %bb.0: -; SSE-NEXT: pxor %xmm2, %xmm2 -; SSE-NEXT: pcmpgtw %xmm0, %xmm2 -; SSE-NEXT: pandn %xmm1, %xmm2 -; SSE-NEXT: movdqa %xmm2, %xmm0 +; SSE-NEXT: psraw $15, %xmm0 +; SSE-NEXT: pandn %xmm1, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: not_signbit_mask_swap_v8i16: ; AVX: # %bb.0: -; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX-NEXT: vpcmpgtw %xmm0, %xmm2, %xmm0 +; AVX-NEXT: vpsraw $15, %xmm0, %xmm0 ; AVX-NEXT: vpandn %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq ; -; AVX512F-LABEL: not_signbit_mask_swap_v8i16: -; AVX512F: # %bb.0: -; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX512F-NEXT: vpcmpgtw %xmm0, %xmm2, %xmm0 -; AVX512F-NEXT: vpandn %xmm1, %xmm0, %xmm0 -; AVX512F-NEXT: retq -; -; AVX512DQBW-LABEL: not_signbit_mask_swap_v8i16: -; AVX512DQBW: # %bb.0: -; AVX512DQBW-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX512DQBW-NEXT: vpcmpnltw %xmm2, %xmm0, %k1 -; AVX512DQBW-NEXT: vmovdqu16 %xmm1, %xmm0 {%k1} {z} -; AVX512DQBW-NEXT: retq +; AVX512-LABEL: not_signbit_mask_swap_v8i16: +; AVX512: # %bb.0: +; AVX512-NEXT: vpsraw $15, %xmm0, %xmm0 +; AVX512-NEXT: vpandn %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: retq %cond = icmp slt <8 x i16> %a, zeroinitializer %r = select <8 x i1> %cond, <8 x i16> zeroinitializer, <8 x i16> %b ret <8 x i16> %r @@ -1212,38 +1157,31 @@ define <8 x i32> @not_signbit_mask_v8i32(<8 x i32> %a, <8 x i32> %b) { define <8 x i32> @not_signbit_mask_swap_v8i32(<8 x i32> %a, <8 x i32> %b) { ; SSE-LABEL: not_signbit_mask_swap_v8i32: ; SSE: # %bb.0: -; SSE-NEXT: pxor %xmm4, %xmm4 -; SSE-NEXT: pxor %xmm5, %xmm5 -; SSE-NEXT: pcmpgtd %xmm0, %xmm5 -; SSE-NEXT: pandn %xmm2, %xmm5 -; SSE-NEXT: pcmpgtd %xmm1, %xmm4 -; SSE-NEXT: pandn %xmm3, %xmm4 -; SSE-NEXT: movdqa %xmm5, %xmm0 -; SSE-NEXT: movdqa %xmm4, %xmm1 +; SSE-NEXT: psrad $31, %xmm0 +; SSE-NEXT: pandn %xmm2, %xmm0 +; SSE-NEXT: psrad $31, %xmm1 +; SSE-NEXT: pandn %xmm3, %xmm1 ; SSE-NEXT: retq ; ; AVX1-LABEL: not_signbit_mask_swap_v8i32: ; AVX1: # %bb.0: -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 -; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 -; AVX1-NEXT: vpcmpgtd %xmm2, %xmm3, %xmm2 -; AVX1-NEXT: vpcmpgtd %xmm0, %xmm3, %xmm0 -; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: vpsrad $31, %xmm0, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 ; AVX1-NEXT: vandnps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: retq ; ; AVX2-LABEL: not_signbit_mask_swap_v8i32: ; AVX2: # %bb.0: -; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX2-NEXT: vpcmpgtd %ymm0, %ymm2, %ymm0 +; AVX2-NEXT: vpsrad $31, %ymm0, %ymm0 ; AVX2-NEXT: vpandn %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: not_signbit_mask_swap_v8i32: ; AVX512: # %bb.0: -; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX512-NEXT: vpcmpnltd %ymm2, %ymm0, %k1 -; AVX512-NEXT: vmovdqa32 %ymm1, %ymm0 {%k1} {z} +; AVX512-NEXT: vpsrad $31, %ymm0, %ymm0 +; AVX512-NEXT: vpandn %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq %cond = icmp slt <8 x i32> %a, zeroinitializer %r = select <8 x i1> %cond, <8 x i32> zeroinitializer, <8 x i32> %b -- 2.7.4