From 25255ddcadf2a8d4edaa1d822c33151a95f52f04 Mon Sep 17 00:00:00 2001 From: Zongdong Jiao Date: Tue, 29 Jan 2019 19:17:26 +0800 Subject: [PATCH] hdmitx: correct g12 rx_sense detect setting [1/1] PD#SWPL-4684 Problem: g12 rx_sense can't work well Solution: correct g12 rx_sense detect setting Verify: G12/U212 Change-Id: I26ae578bdf278592956dff092e60d13faf4905bf Signed-off-by: Zongdong Jiao --- drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c index 13e5f54..b93ab08 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c @@ -4991,6 +4991,14 @@ static int hdmitx_tmds_rxsense(void) struct hdmitx_dev *hdev = get_hdmitx_device(); switch (hdev->chip_type) { + case MESON_CPU_ID_G12A: + case MESON_CPU_ID_G12B: + hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL0, 1, 16, 1); + hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL3, 1, 23, 1); + hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL3, 0, 24, 1); + hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL3, 7, 20, 3); + ret = hd_read_reg(P_HHI_HDMI_PHY_CNTL2) & 0x1; + break; case MESON_CPU_ID_GXBB: curr0 = hd_read_reg(P_HHI_HDMI_PHY_CNTL0); curr3 = hd_read_reg(P_HHI_HDMI_PHY_CNTL3); -- 2.7.4