From 250ad910e830091c0c83e2e7b069963cf4fc2cfa Mon Sep 17 00:00:00 2001 From: Hong Guo Date: Wed, 23 May 2018 16:50:53 +0800 Subject: [PATCH] CPUFREQ: add cpufreq dts config for g12b. PD#165090: cpufreq: add cpufreq dts config for g12b. Change-Id: I5478b967d14a574a3b435743363cdb23969b38e9 Signed-off-by: Hong Guo --- arch/arm64/boot/dts/amlogic/g12b_pxp.dts | 61 +++++++++++- arch/arm64/boot/dts/amlogic/mesong12b.dtsi | 147 ++++++++++++++++++++++++++--- drivers/amlogic/clk/g12a/g12a_clk-pll.c | 19 +++- 3 files changed, 207 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/g12b_pxp.dts b/arch/arm64/boot/dts/amlogic/g12b_pxp.dts index 3e54f70..56ee574 100644 --- a/arch/arm64/boot/dts/amlogic/g12b_pxp.dts +++ b/arch/arm64/boot/dts/amlogic/g12b_pxp.dts @@ -387,11 +387,59 @@ }; }; + cpu_opp_table1: cpu_opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <751000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <751000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <751000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <751000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <771000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <771000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <791000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <821000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <861000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <891000>; + }; + opp10 { + opp-hz = /bits/ 64 <1896000000>; + opp-microvolt = <981000>; + }; + }; + cpufreq-meson { compatible = "amlogic, cpufreq-meson"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm_ao_d_pins3>; - status = "okay"; + status = "disable"; }; @@ -408,7 +456,12 @@ &pwm_AO_cd { status = "okay"; - }; +}; + +&pwm_ab { + status = "okay"; +}; + &audiobus { aml_tdma: tdma { diff --git a/arch/arm64/boot/dts/amlogic/mesong12b.dtsi b/arch/arm64/boot/dts/amlogic/mesong12b.dtsi index 0b84e81a..a487166 100644 --- a/arch/arm64/boot/dts/amlogic/mesong12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesong12b.dtsi @@ -66,6 +66,16 @@ enable-method = "psci"; //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; + clocks = <&clkc CLKID_CPU_CLK>, + <&clkc CLKID_CPU_FCLK_P>, + <&clkc CLKID_SYS1_PLL>; + clock-names = "core_clk", + "low_freq_clk_parent", + "high_freq_clk_parent"; + operating-points-v2 = <&cpu_opp_table0>; + cpu-supply = <&vddcpu0>; + voltage-tolerance = <0>; + clock-latency = <50000>; }; CPU1:cpu@1 { @@ -74,6 +84,16 @@ reg = <0x0 0x1>; enable-method = "psci"; sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; + clocks = <&clkc CLKID_CPU_CLK>, + <&clkc CLKID_CPU_FCLK_P>, + <&clkc CLKID_SYS1_PLL>; + clock-names = "core_clk", + "low_freq_clk_parent", + "high_freq_clk_parent"; + operating-points-v2 = <&cpu_opp_table0>; + cpu-supply = <&vddcpu0>; + voltage-tolerance = <0>; + clock-latency = <50000>; }; CPU2:cpu@100 { @@ -83,6 +103,17 @@ enable-method = "psci"; //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; sched-energy-costs = <&CPU_COST_A73 &CLUSTER_COST_A73>; + clocks = <&clkc CLKID_CPUB_CLK>, + <&clkc CLKID_CPUB_FCLK_P>, + <&clkc CLKID_SYS_PLL>; + clock-names = "core_clk", + "low_freq_clk_parent", + "high_freq_clk_parent"; + operating-points-v2 = <&cpu_opp_table1>; + cpu-supply = <&vddcpu1>; + voltage-tolerance = <0>; + clock-latency = <50000>; + }; CPU3:cpu@101 { @@ -92,6 +123,17 @@ enable-method = "psci"; //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; sched-energy-costs = <&CPU_COST_A73 &CLUSTER_COST_A73>; + clocks = <&clkc CLKID_CPUB_CLK>, + <&clkc CLKID_CPUB_FCLK_P>, + <&clkc CLKID_SYS_PLL>; + clock-names = "core_clk", + "low_freq_clk_parent", + "high_freq_clk_parent"; + operating-points-v2 = <&cpu_opp_table1>; + cpu-supply = <&vddcpu1>; + voltage-tolerance = <0>; + clock-latency = <50000>; + }; CPU4:cpu@102 { @@ -101,6 +143,16 @@ enable-method = "psci"; //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; sched-energy-costs = <&CPU_COST_A73 &CLUSTER_COST_A73>; + clocks = <&clkc CLKID_CPUB_CLK>, + <&clkc CLKID_CPUB_FCLK_P>, + <&clkc CLKID_SYS_PLL>; + clock-names = "core_clk", + "low_freq_clk_parent", + "high_freq_clk_parent"; + operating-points-v2 = <&cpu_opp_table1>; + cpu-supply = <&vddcpu1>; + voltage-tolerance = <0>; + clock-latency = <50000>; }; CPU5:cpu@103 { @@ -110,6 +162,16 @@ enable-method = "psci"; //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; sched-energy-costs = <&CPU_COST_A73 &CLUSTER_COST_A73>; + clocks = <&clkc CLKID_CPUB_CLK>, + <&clkc CLKID_CPUB_FCLK_P>, + <&clkc CLKID_SYS_PLL>; + clock-names = "core_clk", + "low_freq_clk_parent", + "high_freq_clk_parent"; + operating-points-v2 = <&cpu_opp_table1>; + cpu-supply = <&vddcpu1>; + voltage-tolerance = <0>; + clock-latency = <50000>; }; idle-states { @@ -1585,25 +1647,28 @@ vddcpu0: pwmao_d-regulator { compatible = "pwm-regulator"; - pwms = <&pwm_AO_cd MESON_PWM_1 1210 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_ao_d_pins3>; + pwms = <&pwm_AO_cd MESON_PWM_1 1250 0>; regulator-name = "vddcpu0"; - regulator-min-microvolt = <731000>; - regulator-max-microvolt = <1011000>; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; regulator-always-on; - max-duty-cycle = <1210>; + max-duty-cycle = <1250>; /* Voltage Duty-Cycle */ - voltage-table = <1011000 0>, + voltage-table = <1022000 0>, + <1011000 3>, <1001000 6>, - <991000 9>, - <981000 12>, + <991000 10>, + <981000 13>, <971000 16>, - <961000 19>, + <961000 20>, <951000 23>, <941000 26>, - <931000 29>, + <931000 30>, <921000 33>, <911000 36>, - <901000 39>, + <901000 40>, <891000 43>, <881000 46>, <871000 50>, @@ -1614,13 +1679,59 @@ <821000 67>, <811000 70>, <801000 73>, - <791000 77>, + <791000 76>, <781000 80>, - <771000 84>, - <761000 87>, + <771000 83>, + <761000 86>, <751000 90>, - <741000 94>, - <731000 100>; + <741000 93>, + <731000 96>, + <721000 100>; + status = "okay"; + }; + + vddcpu1: pwmab_a-regulator { + compatible = "pwm-regulator"; + pinctrl-names = "default"; + pinctrl-1 = <&pwm_a_e2>; + pwms = <&pwm_ab MESON_PWM_0 1250 0>; + regulator-name = "vddcpu1"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + regulator-always-on; + max-duty-cycle = <1250>; + /* Voltage Duty-Cycle */ + voltage-table = <1022000 0>, + <1011000 3>, + <1001000 6>, + <991000 10>, + <981000 13>, + <971000 16>, + <961000 20>, + <951000 23>, + <941000 26>, + <931000 30>, + <921000 33>, + <911000 36>, + <901000 40>, + <891000 43>, + <881000 46>, + <871000 50>, + <861000 53>, + <851000 56>, + <841000 60>, + <831000 63>, + <821000 67>, + <811000 70>, + <801000 73>, + <791000 76>, + <781000 80>, + <771000 83>, + <761000 86>, + <751000 90>, + <741000 93>, + <731000 96>, + <721000 100>; status = "okay"; }; @@ -1751,6 +1862,12 @@ function = "cec_ao"; }; }; + pwm_a_e2: pwm_a_e2 { + mux { + groups = "pwm_a_e2"; + function = "pwm_a_gpioe"; + }; + }; }; &pinctrl_periphs { diff --git a/drivers/amlogic/clk/g12a/g12a_clk-pll.c b/drivers/amlogic/clk/g12a/g12a_clk-pll.c index 6f98525..660428b 100644 --- a/drivers/amlogic/clk/g12a/g12a_clk-pll.c +++ b/drivers/amlogic/clk/g12a/g12a_clk-pll.c @@ -70,6 +70,12 @@ #define G12A_SYS_PLL_CNTL4 0x88770290 #define G12A_SYS_PLL_CNTL5 0x39272000 +#define G12A_SYS1_PLL_CNTL1 0x00000000 +#define G12A_SYS1_PLL_CNTL2 0x00000000 +#define G12A_SYS1_PLL_CNTL3 0x48681c00 +#define G12A_SYS1_PLL_CNTL4 0x88770290 +#define G12A_SYS1_PLL_CNTL5 0x39272000 + #define G12A_GP0_PLL_CNTL1 0x00000000 #define G12A_GP0_PLL_CNTL2 0x00000000 #define G12A_GP0_PLL_CNTL3 0x48681c00 @@ -255,6 +261,16 @@ static int meson_g12a_pll_set_rate(struct clk_hw *hw, unsigned long rate, writel(G12A_SYS_PLL_CNTL5, cntlbase + (u64)5*4); writel(G12A_PLL_CNTL6, cntlbase + (u64)6*4); udelay(10); + } else if (!strcmp(clk_hw_get_name(hw), "sys1_pll")) { + writel((readl(cntlbase) | MESON_PLL_RESET) + & (~MESON_PLL_ENABLE), cntlbase); + writel(G12A_SYS1_PLL_CNTL1, cntlbase + (u64)1*4); + writel(G12A_SYS1_PLL_CNTL2, cntlbase + (u64)2*4); + writel(G12A_SYS1_PLL_CNTL3, cntlbase + (u64)3*4); + writel(G12A_SYS1_PLL_CNTL4, cntlbase + (u64)4*4); + writel(G12A_SYS1_PLL_CNTL5, cntlbase + (u64)5*4); + writel(G12A_PLL_CNTL6, cntlbase + (u64)6*4); + udelay(10); } else if (!strcmp(clk_hw_get_name(hw), "gp0_pll")) { writel((readl(cntlbase) | MESON_PLL_RESET) & (~MESON_PLL_ENABLE), cntlbase); @@ -364,7 +380,8 @@ static int meson_g12a_pll_enable(struct clk_hw *hw) if (!strcmp(clk_hw_get_name(hw), "gp0_pll") || !strcmp(clk_hw_get_name(hw), "hifi_pll") || !strcmp(clk_hw_get_name(hw), "pcie_pll") - || !strcmp(clk_hw_get_name(hw), "sys_pll")) { + || !strcmp(clk_hw_get_name(hw), "sys_pll") + || !strcmp(clk_hw_get_name(hw), "sys1_pll")) { void *cntlbase = pll->base + p->reg_off; if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) { -- 2.7.4