From 2481f26ac3f228cc085d4d68ee72dadc07afa48f Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 7 Apr 2020 16:33:58 -0400 Subject: [PATCH] CodeGen: Use Register in TargetFrameLowering --- llvm/include/llvm/CodeGen/TargetFrameLowering.h | 8 +++--- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 2 +- llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | 4 +-- llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp | 2 +- llvm/lib/CodeGen/AsmPrinter/WinException.cpp | 6 ++--- llvm/lib/CodeGen/GCRootLowering.cpp | 2 +- llvm/lib/CodeGen/LiveDebugValues.cpp | 2 +- llvm/lib/CodeGen/PrologEpilogInserter.cpp | 4 +-- llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp | 7 +++--- .../Target/AArch64/AArch64ExpandPseudoInsts.cpp | 2 +- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp | 10 ++++---- llvm/lib/Target/AArch64/AArch64FrameLowering.h | 8 +++--- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/R600FrameLowering.cpp | 5 ++-- llvm/lib/Target/AMDGPU/R600FrameLowering.h | 2 +- llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 2 +- llvm/lib/Target/AMDGPU/R600InstrInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 4 +-- llvm/lib/Target/AMDGPU/SIFrameLowering.h | 2 +- llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | 2 +- llvm/lib/Target/ARM/ARMFrameLowering.cpp | 12 ++++----- llvm/lib/Target/ARM/ARMFrameLowering.h | 4 +-- llvm/lib/Target/ARM/ThumbRegisterInfo.cpp | 4 +-- llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp | 11 ++++---- llvm/lib/Target/Hexagon/HexagonFrameLowering.h | 2 +- llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp | 2 +- llvm/lib/Target/Mips/MipsSEFrameLowering.cpp | 2 +- llvm/lib/Target/Mips/MipsSEFrameLowering.h | 2 +- llvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp | 2 +- llvm/lib/Target/NVPTX/NVPTXFrameLowering.h | 2 +- llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp | 2 +- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 2 +- llvm/lib/Target/RISCV/RISCVFrameLowering.h | 2 +- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 2 +- llvm/lib/Target/Sparc/SparcFrameLowering.cpp | 6 ++--- llvm/lib/Target/Sparc/SparcFrameLowering.h | 2 +- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp | 2 +- llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp | 11 ++++---- llvm/lib/Target/SystemZ/SystemZFrameLowering.h | 4 +-- llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp | 2 +- llvm/lib/Target/X86/X86FrameLowering.cpp | 29 +++++++++++----------- llvm/lib/Target/X86/X86FrameLowering.h | 16 ++++++------ llvm/lib/Target/X86/X86RegisterInfo.cpp | 2 +- 43 files changed, 100 insertions(+), 103 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetFrameLowering.h b/llvm/include/llvm/CodeGen/TargetFrameLowering.h index 177510d..bbf25c5 100644 --- a/llvm/include/llvm/CodeGen/TargetFrameLowering.h +++ b/llvm/include/llvm/CodeGen/TargetFrameLowering.h @@ -283,7 +283,7 @@ public: /// and offset used to reference a frame index location. The offset is /// returned directly, and the base register is returned via FrameReg. virtual int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const; + Register &FrameReg) const; /// Same as \c getFrameIndexReference, except that the stack pointer (as /// opposed to the frame pointer) will be the preferred value for \p @@ -292,7 +292,7 @@ public: /// offset is only guaranteed to be valid with respect to the value of SP at /// the end of the prologue. virtual int getFrameIndexReferencePreferSP(const MachineFunction &MF, int FI, - unsigned &FrameReg, + Register &FrameReg, bool IgnoreSPUpdates) const { // Always safe to dispatch to getFrameIndexReference. return getFrameIndexReference(MF, FI, FrameReg); @@ -305,7 +305,7 @@ public: int FI) const { // By default, dispatch to getFrameIndexReference. Interested targets can // override this. - unsigned FrameReg; + Register FrameReg; return getFrameIndexReference(MF, FI, FrameReg); } @@ -427,7 +427,7 @@ public: /// Return initial CFA register value i.e. the one valid at the beginning of /// the function (before any stack operations). - virtual unsigned getInitialCFARegister(const MachineFunction &MF) const; + virtual Register getInitialCFARegister(const MachineFunction &MF) const; /// Return the frame base information to be encoded in the DWARF subprogram /// debug info. diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 60f2073..b7bd6c9 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -923,7 +923,7 @@ static bool emitDebugValueComment(const MachineInstr *MI, AsmPrinter &AP) { OS << "!target-index(" << Op.getIndex() << "," << Op.getOffset() << ")"; return true; } else { - unsigned Reg; + Register Reg; if (MI->getOperand(0).isReg()) { Reg = MI->getOperand(0).getReg(); } else { diff --git a/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp index 814273c..ca349cb 100644 --- a/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp @@ -1182,7 +1182,7 @@ void CodeViewDebug::collectVariableInfoFromMFTable( } // Get the frame register used and the offset. - unsigned FrameReg = 0; + Register FrameReg; int FrameOffset = TFI->getFrameIndexReference(*Asm->MF, VI.Slot, FrameReg); uint16_t CVReg = TRI->getCodeViewRegNum(FrameReg); @@ -2257,7 +2257,7 @@ TypeIndex CodeViewDebug::lowerCompleteTypeClass(const DICompositeType *Ty) { // MSVC appears to set this flag by searching any destructor or method with // FunctionOptions::Constructor among the emitted members. Clang AST has all - // the members, however special member functions are not yet emitted into + // the members, however special member functions are not yet emitted into // debug information. For now checking a class's non-triviality seems enough. // FIXME: not true for a nested unnamed struct. if (isNonTrivial(Ty)) diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp index c3b2a0d..34d808d 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp @@ -674,7 +674,7 @@ DIE *DwarfCompileUnit::constructVariableDIEImpl(const DbgVariable &DV, DIELoc *Loc = new (DIEValueAllocator) DIELoc; DIEDwarfExpression DwarfExpr(*Asm, *this, *Loc); for (auto &Fragment : DV.getFrameIndexExprs()) { - unsigned FrameReg = 0; + Register FrameReg; const DIExpression *Expr = Fragment.Expr; const TargetFrameLowering *TFI = Asm->MF->getSubtarget().getFrameLowering(); int Offset = TFI->getFrameIndexReference(*Asm->MF, Fragment.FI, FrameReg); diff --git a/llvm/lib/CodeGen/AsmPrinter/WinException.cpp b/llvm/lib/CodeGen/AsmPrinter/WinException.cpp index bbf0e46..dbacce7 100644 --- a/llvm/lib/CodeGen/AsmPrinter/WinException.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/WinException.cpp @@ -336,7 +336,7 @@ const MCExpr *WinException::getOffsetPlusOne(const MCSymbol *OffsetOf, int WinException::getFrameIndexOffset(int FrameIndex, const WinEHFuncInfo &FuncInfo) { const TargetFrameLowering &TFI = *Asm->MF->getSubtarget().getFrameLowering(); - unsigned UnusedReg; + Register UnusedReg; if (Asm->MAI->usesWindowsCFI()) { int Offset = TFI.getFrameIndexReferencePreferSP(*Asm->MF, FrameIndex, UnusedReg, @@ -1011,7 +1011,7 @@ void WinException::emitExceptHandlerTable(const MachineFunction *MF) { int GSCookieOffset = -2; const MachineFrameInfo &MFI = MF->getFrameInfo(); if (MFI.hasStackProtectorIndex()) { - unsigned UnusedReg; + Register UnusedReg; const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); int SSPIdx = MFI.getStackProtectorIndex(); GSCookieOffset = TFI->getFrameIndexReference(*MF, SSPIdx, UnusedReg); @@ -1021,7 +1021,7 @@ void WinException::emitExceptHandlerTable(const MachineFunction *MF) { // TODO(etienneb): Get rid of this value and change it for and assertion. int EHCookieOffset = 9999; if (FuncInfo.EHGuardFrameIndex != INT_MAX) { - unsigned UnusedReg; + Register UnusedReg; const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); int EHGuardIdx = FuncInfo.EHGuardFrameIndex; EHCookieOffset = TFI->getFrameIndexReference(*MF, EHGuardIdx, UnusedReg); diff --git a/llvm/lib/CodeGen/GCRootLowering.cpp b/llvm/lib/CodeGen/GCRootLowering.cpp index 2a85048..03faaab 100644 --- a/llvm/lib/CodeGen/GCRootLowering.cpp +++ b/llvm/lib/CodeGen/GCRootLowering.cpp @@ -297,7 +297,7 @@ void GCMachineCodeAnalysis::FindStackOffsets(MachineFunction &MF) { if (MF.getFrameInfo().isDeadObjectIndex(RI->Num)) { RI = FI->removeStackRoot(RI); } else { - unsigned FrameReg; // FIXME: surely GCRoot ought to store the + Register FrameReg; // FIXME: surely GCRoot ought to store the // register that the offset is from? RI->StackOffset = TFI->getFrameIndexReference(MF, RI->Num, FrameReg); ++RI; diff --git a/llvm/lib/CodeGen/LiveDebugValues.cpp b/llvm/lib/CodeGen/LiveDebugValues.cpp index 9816bd8..530da52 100644 --- a/llvm/lib/CodeGen/LiveDebugValues.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues.cpp @@ -864,7 +864,7 @@ LiveDebugValues::extractSpillBaseRegAndOffset(const MachineInstr &MI) { "Inconsistent memory operand in spill instruction"); int FI = cast(PVal)->getFrameIndex(); const MachineBasicBlock *MBB = MI.getParent(); - unsigned Reg; + Register Reg; int Offset = TFI->getFrameIndexReference(*MBB->getParent(), FI, Reg); return {Reg, Offset}; } diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp index 32e2dee..70dd1d1 100644 --- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -1205,7 +1205,7 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &MF, if (MI.isDebugValue()) { assert(i == 0 && "Frame indices can only appear as the first " "operand of a DBG_VALUE machine instruction"); - unsigned Reg; + Register Reg; unsigned FrameIdx = MI.getOperand(0).getIndex(); unsigned Size = MF.getFrameInfo().getObjectSize(FrameIdx); @@ -1250,7 +1250,7 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &MF, assert((!MI.isDebugValue() || i == 0) && "Frame indicies can only appear as the first operand of a " "DBG_VALUE machine instruction"); - unsigned Reg; + Register Reg; MachineOperand &Offset = MI.getOperand(i + 1); int refOffset = TFI->getFrameIndexReferencePreferSP( MF, MI.getOperand(i).getIndex(), Reg, /*IgnoreSPUpdates*/ false); diff --git a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp index 9d9bc26..b981e96 100644 --- a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp +++ b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp @@ -42,7 +42,8 @@ bool TargetFrameLowering::enableCalleeSaveSkip(const MachineFunction &MF) const /// (in output arg FrameReg). This is the default implementation which /// is overridden for some targets. int TargetFrameLowering::getFrameIndexReference(const MachineFunction &MF, - int FI, unsigned &FrameReg) const { + int FI, + Register &FrameReg) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); @@ -150,8 +151,8 @@ int TargetFrameLowering::getInitialCFAOffset(const MachineFunction &MF) const { llvm_unreachable("getInitialCFAOffset() not implemented!"); } -unsigned TargetFrameLowering::getInitialCFARegister(const MachineFunction &MF) - const { +Register +TargetFrameLowering::getInitialCFARegister(const MachineFunction &MF) const { llvm_unreachable("getInitialCFARegister() not implemented!"); } diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp index 4a0b1b4..381bf86 100644 --- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp +++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp @@ -932,7 +932,7 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB, // almost always point to SP-after-prologue; if not, emit a longer // instruction sequence. int BaseOffset = -AFI->getTaggedBasePointerOffset(); - unsigned FrameReg; + Register FrameReg; StackOffset FrameRegOffset = TFI->resolveFrameOffsetReference( MF, BaseOffset, false /*isFixed*/, false /*isSVE*/, FrameReg, /*PreferFP=*/false, diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index 17b13f6..c29ae29 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -1699,7 +1699,7 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF, /// SP-relative and simple call frames aren't used. int AArch64FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const { + Register &FrameReg) const { return resolveFrameIndexReference( MF, FI, FrameReg, /*PreferFP=*/ @@ -1742,7 +1742,7 @@ int AArch64FrameLowering::getSEHFrameIndexOffset(const MachineFunction &MF, } StackOffset AArch64FrameLowering::resolveFrameIndexReference( - const MachineFunction &MF, int FI, unsigned &FrameReg, bool PreferFP, + const MachineFunction &MF, int FI, Register &FrameReg, bool PreferFP, bool ForSimm) const { const auto &MFI = MF.getFrameInfo(); int64_t ObjectOffset = MFI.getObjectOffset(FI); @@ -1754,7 +1754,7 @@ StackOffset AArch64FrameLowering::resolveFrameIndexReference( StackOffset AArch64FrameLowering::resolveFrameOffsetReference( const MachineFunction &MF, int64_t ObjectOffset, bool isFixed, bool isSVE, - unsigned &FrameReg, bool PreferFP, bool ForSimm) const { + Register &FrameReg, bool PreferFP, bool ForSimm) const { const auto &MFI = MF.getFrameInfo(); const auto *RegInfo = static_cast( MF.getSubtarget().getRegisterInfo()); @@ -2895,7 +2895,7 @@ void TagStoreEdit::emitCode(MachineBasicBlock::iterator &InsertI, Size = LastTagStore.Offset - FirstTagStore.Offset + LastTagStore.Size; DL = TagStores[0].MI->getDebugLoc(); - unsigned Reg; + Register Reg; FrameRegOffset = TFI->resolveFrameOffsetReference( *MF, FirstTagStore.Offset, false /*isFixed*/, false /*isSVE*/, Reg, /*PreferFP=*/false, /*ForSimm=*/true); @@ -3089,7 +3089,7 @@ void AArch64FrameLowering::processFunctionBeforeFrameIndicesReplaced( /// before the update. This is easily retrieved as it is exactly the offset /// that is set in processFunctionBeforeFrameFinalized. int AArch64FrameLowering::getFrameIndexReferencePreferSP( - const MachineFunction &MF, int FI, unsigned &FrameReg, + const MachineFunction &MF, int FI, Register &FrameReg, bool IgnoreSPUpdates) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); if (IgnoreSPUpdates) { diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.h b/llvm/lib/Target/AArch64/AArch64FrameLowering.h index e423fa7..0134d3f 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.h +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.h @@ -39,13 +39,13 @@ public: bool canUseAsPrologue(const MachineBasicBlock &MBB) const override; int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const override; + Register &FrameReg) const override; StackOffset resolveFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg, bool PreferFP, + Register &FrameReg, bool PreferFP, bool ForSimm) const; StackOffset resolveFrameOffsetReference(const MachineFunction &MF, int64_t ObjectOffset, bool isFixed, - bool isSVE, unsigned &FrameReg, + bool isSVE, Register &FrameReg, bool PreferFP, bool ForSimm) const; bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, @@ -87,7 +87,7 @@ public: unsigned getWinEHFuncletFrameSize(const MachineFunction &MF) const; int getFrameIndexReferencePreferSP(const MachineFunction &MF, int FI, - unsigned &FrameReg, + Register &FrameReg, bool IgnoreSPUpdates) const override; int getNonLocalFrameIndexReference(const MachineFunction &MF, int FI) const override; diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp index 345cbbf..282fe6a 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp @@ -486,7 +486,7 @@ void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); bool Tagged = MI.getOperand(FIOperandNum).getTargetFlags() & AArch64II::MO_TAGGED; - unsigned FrameReg; + Register FrameReg; // Special handling of dbg_value, stackmap and patchpoint instructions. if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP || diff --git a/llvm/lib/Target/AMDGPU/R600FrameLowering.cpp b/llvm/lib/Target/AMDGPU/R600FrameLowering.cpp index d2fe3c9..c568a4a 100644 --- a/llvm/lib/Target/AMDGPU/R600FrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/R600FrameLowering.cpp @@ -18,9 +18,8 @@ using namespace llvm; R600FrameLowering::~R600FrameLowering() = default; /// \returns The number of registers allocated for \p FI. -int R600FrameLowering::getFrameIndexReference(const MachineFunction &MF, - int FI, - unsigned &FrameReg) const { +int R600FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); const R600RegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); diff --git a/llvm/lib/Target/AMDGPU/R600FrameLowering.h b/llvm/lib/Target/AMDGPU/R600FrameLowering.h index 722d516..b877ecd 100644 --- a/llvm/lib/Target/AMDGPU/R600FrameLowering.h +++ b/llvm/lib/Target/AMDGPU/R600FrameLowering.h @@ -25,7 +25,7 @@ public: void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override {} int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const override; + Register &FrameReg) const override; bool hasFP(const MachineFunction &MF) const override { return false; diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp index b76fd50..e0c63bc 100644 --- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -1548,7 +1548,7 @@ SDValue R600TargetLowering::lowerFrameIndex(SDValue Op, FrameIndexSDNode *FIN = cast(Op); unsigned FrameIndex = FIN->getIndex(); - unsigned IgnoredFrameReg; + Register IgnoredFrameReg; unsigned Offset = TFL->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg); return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), SDLoc(Op), diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp index e1da6e4..088cf16 100644 --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -1224,7 +1224,7 @@ int R600InstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const { const R600Subtarget &ST = MF.getSubtarget(); const R600FrameLowering *TFL = ST.getFrameLowering(); - unsigned IgnoredFrameReg; + Register IgnoredFrameReg; Offset = TFL->getFrameIndexReference(MF, -1, IgnoredFrameReg); return getIndirectIndexBegin(MF) + Offset; diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index 46515ae..93f79f6 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -809,7 +809,7 @@ void SIFrameLowering::emitEpilogue(MachineFunction &MF, if (ScratchExecCopy != AMDGPU::NoRegister) { // FIXME: Split block and make terminator. unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; - unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; + MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; BuildMI(MBB, MBBI, DL, TII->get(ExecMov), Exec) .addReg(ScratchExecCopy, RegState::Kill); } @@ -844,7 +844,7 @@ static bool allSGPRSpillsAreDead(const MachineFrameInfo &MFI, #endif int SIFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const { + Register &FrameReg) const { const SIRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); FrameReg = RI->getFrameRegister(MF); diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.h b/llvm/lib/Target/AMDGPU/SIFrameLowering.h index 7314057..5bd3b0b 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.h +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.h @@ -32,7 +32,7 @@ public: void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const override; + Register &FrameReg) const override; void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS = nullptr) const override; diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp index c60e43b..fac0ac4 100644 --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -754,7 +754,7 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, assert(!AFI->isThumb1OnlyFunction() && "This eliminateFrameIndex does not support Thumb1!"); int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); - unsigned FrameReg; + Register FrameReg; int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index 76e5162..0acaeaa 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -866,16 +866,14 @@ void ARMFrameLowering::emitEpilogue(MachineFunction &MF, /// debug info. It's the same as what we use for resolving the code-gen /// references for now. FIXME: This can go wrong when references are /// SP-relative and simple call frames aren't used. -int -ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const { +int ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const { return ResolveFrameIndexReference(MF, FI, FrameReg, 0); } -int -ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF, - int FI, unsigned &FrameReg, - int SPAdj) const { +int ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF, + int FI, Register &FrameReg, + int SPAdj) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); const ARMBaseRegisterInfo *RegInfo = static_cast( MF.getSubtarget().getRegisterInfo()); diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.h b/llvm/lib/Target/ARM/ARMFrameLowering.h index f30f389..e46a873 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.h +++ b/llvm/lib/Target/ARM/ARMFrameLowering.h @@ -50,9 +50,9 @@ public: bool hasReservedCallFrame(const MachineFunction &MF) const override; bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override; int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const override; + Register &FrameReg) const override; int ResolveFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg, int SPAdj) const; + Register &FrameReg, int SPAdj) const; void getCalleeSaves(const MachineFunction &MF, BitVector &SavedRegs) const override; diff --git a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp index b0ba58d..2e6901d 100644 --- a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp @@ -458,12 +458,12 @@ void ThumbRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, return ARMBaseRegisterInfo::eliminateFrameIndex(II, SPAdj, FIOperandNum, RS); - unsigned VReg = 0; + Register VReg; const ARMBaseInstrInfo &TII = *STI.getInstrInfo(); DebugLoc dl = MI.getDebugLoc(); MachineInstrBuilder MIB(*MBB.getParent(), &MI); - unsigned FrameReg; + Register FrameReg; int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); const ARMFrameLowering *TFI = getFrameLowering(MF); int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index 5979b63..1a3a0af 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -1103,7 +1103,7 @@ void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB, // Instead, get the offset (relative to the FP) directly. Offset = MFI.getObjectOffset(F->getFrameIdx()); } else { - unsigned FrameReg; + Register FrameReg; Offset = getFrameIndexReference(MF, F->getFrameIdx(), FrameReg); } // Subtract 8 to make room for R30 and R31, which are added above. @@ -1257,7 +1257,8 @@ static const char *getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType, } int HexagonFrameLowering::getFrameIndexReference(const MachineFunction &MF, - int FI, unsigned &FrameReg) const { + int FI, + Register &FrameReg) const { auto &MFI = MF.getFrameInfo(); auto &HRI = *MF.getSubtarget().getRegisterInfo(); @@ -1268,9 +1269,9 @@ int HexagonFrameLowering::getFrameIndexReference(const MachineFunction &MF, auto &HMFI = *MF.getInfo(); unsigned FrameSize = MFI.getStackSize(); - unsigned SP = HRI.getStackRegister(); - unsigned FP = HRI.getFrameRegister(); - unsigned AP = HMFI.getStackAlignBasePhysReg(); + Register SP = HRI.getStackRegister(); + Register FP = HRI.getFrameRegister(); + Register AP = HMFI.getStackAlignBasePhysReg(); // It may happen that AP will be absent even HasAlloca && HasExtraAlign // is true. HasExtraAlign may be set because of vector spills, without // aligned locals or aligned outgoing function arguments. Since vector diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.h b/llvm/lib/Target/Hexagon/HexagonFrameLowering.h index 5949acb..87d385e 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.h @@ -83,7 +83,7 @@ public: } int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const override; + Register &FrameReg) const override; bool hasFP(const MachineFunction &MF) const override; const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries) diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp index 2cb3f7c..52f2479 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -203,7 +203,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, auto &HII = *HST.getInstrInfo(); auto &HFI = *HST.getFrameLowering(); - unsigned BP = 0; + Register BP; int FI = MI.getOperand(FIOp).getIndex(); // Select the base pointer (BP) and calculate the actual offset from BP // to the beginning of the object at index FI. diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp index e0f4f9e..ffcea51 100644 --- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -776,7 +776,7 @@ void MipsSEFrameLowering::emitInterruptEpilogueStub( int MipsSEFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const { + Register &FrameReg) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); MipsABIInfo ABI = STI.getABI(); diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.h b/llvm/lib/Target/Mips/MipsSEFrameLowering.h index 6c586c4..c818a65 100644 --- a/llvm/lib/Target/Mips/MipsSEFrameLowering.h +++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.h @@ -28,7 +28,7 @@ public: void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const override; + Register &FrameReg) const override; bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, diff --git a/llvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp index 2aad490..c533921 100644 --- a/llvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp @@ -65,7 +65,7 @@ void NVPTXFrameLowering::emitPrologue(MachineFunction &MF, int NVPTXFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const { + Register &FrameReg) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); FrameReg = NVPTX::VRDepot; return MFI.getObjectOffset(FI) - getOffsetOfLocalArea(); diff --git a/llvm/lib/Target/NVPTX/NVPTXFrameLowering.h b/llvm/lib/Target/NVPTX/NVPTXFrameLowering.h index 2e58eb7..a80297a 100644 --- a/llvm/lib/Target/NVPTX/NVPTXFrameLowering.h +++ b/llvm/lib/Target/NVPTX/NVPTXFrameLowering.h @@ -25,7 +25,7 @@ public: void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const override; + Register &FrameReg) const override; MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp b/llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp index 0ace176..b4b5d2b 100644 --- a/llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp @@ -67,7 +67,7 @@ bool NVPTXPrologEpilogPass::runOnMachineFunction(MachineFunction &MF) { if (MI.isDebugValue()) { assert(i == 0 && "Frame indices can only appear as the first " "operand of a DBG_VALUE machine instruction"); - unsigned Reg; + Register Reg; int64_t Offset = TFI.getFrameIndexReference(MF, MI.getOperand(0).getIndex(), Reg); MI.getOperand(0).ChangeToRegister(Reg, /*isDef=*/false); diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index 0caafdd..915889a 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -461,7 +461,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const { + Register &FrameReg) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); const auto *RVFI = MF.getInfo(); diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.h b/llvm/lib/Target/RISCV/RISCVFrameLowering.h index 3a3675e..1517c84 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.h +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.h @@ -30,7 +30,7 @@ public: void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const override; + Register &FrameReg) const override; void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override; diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index 05f1b22..51044a2 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -149,7 +149,7 @@ void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, DebugLoc DL = MI.getDebugLoc(); int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); - unsigned FrameReg; + Register FrameReg; int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + MI.getOperand(FIOperandNum + 1).getImm(); diff --git a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp index 6bb3a51..8d84246 100644 --- a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp @@ -257,9 +257,9 @@ bool SparcFrameLowering::hasFP(const MachineFunction &MF) const { MFI.isFrameAddressTaken(); } - -int SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const { +int SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, + int FI, + Register &FrameReg) const { const SparcSubtarget &Subtarget = MF.getSubtarget(); const MachineFrameInfo &MFI = MF.getFrameInfo(); const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); diff --git a/llvm/lib/Target/Sparc/SparcFrameLowering.h b/llvm/lib/Target/Sparc/SparcFrameLowering.h index 8e6001d..3ec9dc8 100644 --- a/llvm/lib/Target/Sparc/SparcFrameLowering.h +++ b/llvm/lib/Target/Sparc/SparcFrameLowering.h @@ -39,7 +39,7 @@ public: RegScavenger *RS = nullptr) const override; int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const override; + Register &FrameReg) const override; /// targetHandlesStackFrameRounding - Returns true if the target is /// responsible for rounding up the stack frame (probably at emitPrologue diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp index 19a90e98..990dbe2 100644 --- a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -173,7 +173,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, const SparcSubtarget &Subtarget = MF.getSubtarget(); const SparcFrameLowering *TFI = getFrameLowering(MF); - unsigned FrameReg; + Register FrameReg; int Offset; Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg); diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp index 0f43ccf..314ac14 100644 --- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp @@ -347,9 +347,8 @@ processFunctionBeforeFrameFinalized(MachineFunction &MF, // Emit instructions before MBBI (in MBB) to add NumBytes to Reg. static void emitIncrement(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MBBI, - const DebugLoc &DL, - unsigned Reg, int64_t NumBytes, + MachineBasicBlock::iterator &MBBI, const DebugLoc &DL, + Register Reg, int64_t NumBytes, const TargetInstrInfo *TII) { while (NumBytes) { unsigned Opcode; @@ -521,7 +520,7 @@ void SystemZFrameLowering::emitPrologue(MachineFunction &MF, // Add CFI for the this save. unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); - unsigned IgnoredFrameReg; + Register IgnoredFrameReg; int64_t Offset = getFrameIndexReference(MF, Save.getFrameIdx(), IgnoredFrameReg); @@ -600,7 +599,7 @@ SystemZFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { int SystemZFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const { + Register &FrameReg) const { // Our incoming SP is actually SystemZMC::CallFrameSize below the CFA, so // add that difference here. int64_t Offset = @@ -626,7 +625,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, } unsigned SystemZFrameLowering::getRegSpillOffset(MachineFunction &MF, - unsigned Reg) const { + Register Reg) const { bool IsVarArg = MF.getFunction().isVarArg(); bool BackChain = MF.getFunction().hasFnAttribute("backchain"); bool SoftFloat = MF.getSubtarget().hasSoftFloat(); diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.h b/llvm/lib/Target/SystemZ/SystemZFrameLowering.h index 5b7ade1..b23f88f 100644 --- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.h +++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.h @@ -46,7 +46,7 @@ public: bool hasFP(const MachineFunction &MF) const override; bool hasReservedCallFrame(const MachineFunction &MF) const override; int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const override; + Register &FrameReg) const override; MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override; @@ -54,7 +54,7 @@ public: // Return the byte offset from the incoming stack pointer of Reg's // ABI-defined save slot. Return 0 if no slot is defined for Reg. Adjust // the offset in case MF has packed-stack. - unsigned getRegSpillOffset(MachineFunction &MF, unsigned Reg) const; + unsigned getRegSpillOffset(MachineFunction &MF, Register Reg) const; // Get or create the frame index of where the old frame pointer is stored. int getOrCreateFramePointerSaveIndex(MachineFunction &MF) const; diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp index 0d5e7af..bb79eb3 100644 --- a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp @@ -267,7 +267,7 @@ SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, // Decompose the frame index into a base and offset. int FrameIndex = MI->getOperand(FIOperandNum).getIndex(); - unsigned BasePtr; + Register BasePtr; int64_t Offset = (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr) + MI->getOperand(FIOperandNum + 1).getImm()); diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp index 6ada321..4a323d8 100644 --- a/llvm/lib/Target/X86/X86FrameLowering.cpp +++ b/llvm/lib/Target/X86/X86FrameLowering.cpp @@ -1561,7 +1561,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF, // into the registration node so that the runtime will restore it for us. if (!MBB.isCleanupFuncletEntry()) { assert(Personality == EHPersonality::MSVC_CXX); - unsigned FrameReg; + Register FrameReg; int FI = MF.getWinEHFuncInfo()->EHRegNodeFrameIndex; int64_t EHRegOffset = getFrameIndexReference(MF, FI, FrameReg); // ESP is the first field, so no extra displacement is needed. @@ -1580,7 +1580,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF, if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) { if (X86::FR64RegClass.contains(Reg)) { int Offset; - unsigned IgnoredFrameReg; + Register IgnoredFrameReg; if (IsWin64Prologue && IsFunclet) Offset = getWin64EHFrameIndexRef(MF, FI, IgnoredFrameReg); else @@ -1655,7 +1655,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF, // it recovers the frame pointer from the base pointer rather than the // other way around. unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr; - unsigned UsedReg; + Register UsedReg; int Offset = getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg); assert(UsedReg == BasePtr); @@ -1732,7 +1732,7 @@ static bool isFuncletReturnInstr(MachineInstr &MI) { unsigned X86FrameLowering::getPSPSlotOffsetFromSP(const MachineFunction &MF) const { const WinEHFuncInfo &Info = *MF.getWinEHFuncInfo(); - unsigned SPReg; + Register SPReg; int Offset = getFrameIndexReferencePreferSP(MF, Info.PSPSymFrameIdx, SPReg, /*IgnoreSPUpdates*/ true); assert(Offset >= 0 && SPReg == TRI->getStackRegister()); @@ -1947,7 +1947,7 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF, } int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const { + Register &FrameReg) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); bool IsFixed = MFI.isFixedObjectIndex(FI); @@ -2040,8 +2040,8 @@ int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, return Offset + FPDelta; } -int X86FrameLowering::getWin64EHFrameIndexRef(const MachineFunction &MF, - int FI, unsigned &FrameReg) const { +int X86FrameLowering::getWin64EHFrameIndexRef(const MachineFunction &MF, int FI, + Register &FrameReg) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); const X86MachineFunctionInfo *X86FI = MF.getInfo(); const auto& WinEHXMMSlotInfo = X86FI->getWinEHXMMSlotInfo(); @@ -2056,17 +2056,16 @@ int X86FrameLowering::getWin64EHFrameIndexRef(const MachineFunction &MF, } int X86FrameLowering::getFrameIndexReferenceSP(const MachineFunction &MF, - int FI, unsigned &FrameReg, + int FI, Register &FrameReg, int Adjustment) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); FrameReg = TRI->getStackRegister(); return MFI.getObjectOffset(FI) - getOffsetOfLocalArea() + Adjustment; } -int -X86FrameLowering::getFrameIndexReferencePreferSP(const MachineFunction &MF, - int FI, unsigned &FrameReg, - bool IgnoreSPUpdates) const { +int X86FrameLowering::getFrameIndexReferencePreferSP( + const MachineFunction &MF, int FI, Register &FrameReg, + bool IgnoreSPUpdates) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); // Does not include any dynamic realign. @@ -3153,7 +3152,7 @@ MachineBasicBlock::iterator X86FrameLowering::restoreWin32EHStackPointers( .setMIFlag(MachineInstr::FrameSetup); } - unsigned UsedReg; + Register UsedReg; int EHRegOffset = getFrameIndexReference(MF, FI, UsedReg); int EndOffset = -EHRegOffset - EHRegSize; FuncInfo.EHRegNodeEndOffset = EndOffset; @@ -3192,8 +3191,8 @@ int X86FrameLowering::getInitialCFAOffset(const MachineFunction &MF) const { return TRI->getSlotSize(); } -unsigned X86FrameLowering::getInitialCFARegister(const MachineFunction &MF) - const { +Register +X86FrameLowering::getInitialCFARegister(const MachineFunction &MF) const { return TRI->getDwarfRegNum(StackPtr, true); } diff --git a/llvm/lib/Target/X86/X86FrameLowering.h b/llvm/lib/Target/X86/X86FrameLowering.h index c7b4154..700c964 100644 --- a/llvm/lib/Target/X86/X86FrameLowering.h +++ b/llvm/lib/Target/X86/X86FrameLowering.h @@ -98,14 +98,14 @@ public: bool needsFrameIndexResolution(const MachineFunction &MF) const override; int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const override; + Register &FrameReg) const override; - int getWin64EHFrameIndexRef(const MachineFunction &MF, - int FI, unsigned &SPReg) const; - int getFrameIndexReferenceSP(const MachineFunction &MF, - int FI, unsigned &SPReg, int Adjustment) const; + int getWin64EHFrameIndexRef(const MachineFunction &MF, int FI, + Register &SPReg) const; + int getFrameIndexReferenceSP(const MachineFunction &MF, int FI, + Register &SPReg, int Adjustment) const; int getFrameIndexReferencePreferSP(const MachineFunction &MF, int FI, - unsigned &FrameReg, + Register &FrameReg, bool IgnoreSPUpdates) const override; MachineBasicBlock::iterator @@ -178,10 +178,10 @@ public: int getInitialCFAOffset(const MachineFunction &MF) const override; - unsigned getInitialCFARegister(const MachineFunction &MF) const override; + Register getInitialCFARegister(const MachineFunction &MF) const override; /// Return true if the function has a redzone (accessible bytes past the - /// frame of the top of stack function) as part of it's ABI. + /// frame of the top of stack function) as part of it's ABI. bool has128ByteRedZone(const MachineFunction& MF) const; private: diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index 22becf4..1c9295c 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -722,7 +722,7 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, // Determine base register and offset. int FIOffset; - unsigned BasePtr; + Register BasePtr; if (MI.isReturn()) { assert((!needsStackRealignment(MF) || MF.getFrameInfo().isFixedObjectIndex(FrameIndex)) && -- 2.7.4